1 research outputs found
Architecture for real time continuous sorting on large width data volume for fpga based applications
In engineering applications sorting is an important and widely studied
problem where execution speed and resources used for computation are of extreme
importance, especially if we think about real time data processing. Most of the
traditional sorting techniques compute the process after receiving all of the
data and hence the process needs large amount of resources for data storage.
So, suitable design strategy needs to be adopted if we wish to sort a large
amount of data in real time, which essential means higher speed of process
execution and utilization of fewer resources in most of the cases. This paper
proposes a single chip scalable architecture based on Field Programmable Gate
Array(FPGA), for a modified counting sort algorithm where data acquisition and
sorting is being done in real time scenario. Our design promises to work
efficiently, where data can be accepted in the run time scenario without any
need of prior storage of data and also the execution speed of our algorithm is
invariant to the length of the data stream. The proposed design is implemented
and verified on Spartan 3E(XC3S500E-FG320) FPGA system. The results prove that
our design is better in terms of some of the design parameters compared to the
existing research works.Comment: 5 pages,RASTM,2011 INDOR