An Integrated 700–1200 MHz Class-F PA with Tunable Harmonic Terminations in 0.13μm CMOS

A fully integrated class-F power amplifier (PA) with reconfigurable harmonic termination over a wide range of frequencies is presented. Reconfigurability is achieved by utilizing on-chip transformers as part of the output matching network. In addition, a stacked transistor architecture was used to boost the output power. The PA was fabricated in a 0.13- μm CMOS process and packaged in a 20-pin quad flat no-leads package. It was configured to operate at 700, 900, and 1200 MHz with a maximum measured saturated output power of +24.6 dBm with a power-added efficiency of 48.3%. The measured gain was 16.5 dB and was flat over the entire bandwidth. The total chip area, including pads, is 1.5 mm × 1.5 mm

RF to Millimeter-wave Linear Power Amplifiers in Nanoscale CMOS SOI Technology

The low manufacturing cost, integration capability with baseband and digital circuits, and high operating frequency of nanoscale CMOS technologies have propelled their applications into RF and microwave systems. Implementing fully-integrated RF to millimeter-wave (mm-wave) CMOS power amplifiers (PAs), nevertheless, remains challenging due to the low breakdown voltages of CMOS transistors and the loss from on-chip matching networks. These limitations have reduced the design space of CMOS power amplifiers to narrow-band, low linearity metrics often with insufficient gain, output power, and efficiency. A new topology for implementing power amplifiers based on stacking of CMOS SOI transistors is proposed. The input RF power is coupled to the transistors using on-chip transformers, while the gate terminal of teach transistor is dynamically biased from the output node. The output voltages of the stacked transistors are added constructively to increase the total output voltage swing and output power. Moreover, the stack configuration increases the optimum load impedance of the PA to values close to 50 ohm, leading to power, efficiency and bandwidth enhancements. Practical design issues such as limitation in the number of stacked transistors, gate oxide breakdown, stability, effect of parasitic capacitances on the performance of the PA and large chip areas have also been addressed. Fully-integrated RF to mm-wave frequency CMOS SOI PAs are successfully implemented and measured using the proposed topology

Analysis and Design of a Transmitter for Wireless Communications in CMOS Technology

The number of wireless devices has grown tremendously over the last decade. Great technology improvements and novel transceiver architectures and circuits have enabled an astonishingly expanding set of radio-frequency applications. CMOS technology played a key role in enabling a large-scale diffusion of wireless devices due to its unique advantages in cost and integration. Novel digital-intensive transceivers have taken full advantage of CMOS technology scaling predicted by Moore's law. Die-shrinking has enabled ubiquitous diffusion of low-cost, small form factor and low power wireless devices. However, Radio Frequency (RF) Power Amplifiers (PA) transceiver functionality is historically implemented in a module which is separated from the CMOS core of the transceiver. The PA is traditionally dictating power and battery life of the transceiver, thus justifying its implementation in a tailored technology. By contrast, a fully integrated CMOS transceiver with no external PA would hugely benefit in terms of reduced area and system complexity. In this work, a fully integrated prototype of a Switched-Capacitor Power Amplifier (SCPA) has been implemented in a 28nm CMOS technology. The SCPA provides the functionalities of a PA and of a Radio-Frequency Digital-to-Analog Converter (RF-DAC) in a monolithic CMOS device. The switching output stage of the SCPA enables this circuital topology to reach high efficiencies and offers excellent power handling capabilities. In this work, the properties of the SCPA are analyzed in an extensive and detailed dissertation. Nowadays Wireless Communications operate in a very crowded spectrum, with strict coexistence requirements, thus demanding a strong linearity to the RF-DAC section of the SCPA. A great part of the work of designing a good SCPA is in fact designing a good RF-DAC. To enhance RF-DAC linearity, a precision of the timing of the elements up to the ps range is required. The use of a single core-supply voltage in the whole circuit including the CMOS inverter of the switching output stage enables the use of minimum size devices, improving accuracy and speed in the timing of the elements. The whole circuit operates therefore on low core-supply voltage. Throughout this work, a detailed analysis carefully describes the electromagnetic structures which maximize power and efficiency of low-voltage SCPAs. Due to layout issues subsequent to limited available voltages, however, there is a practical limitation in the maximum achievable power of low-voltage SCPAs. In this work, a Multi-Port Monolithic Power Combiner (PC) is introduced to overcome this limitation and further enhance total achieved system power. The PC sums the power of a collection of SCPAs to a single output, allowing higher output powers at a high efficiency. Benefits, drawbacks and design of SCPA PCs are discussed in this work. The implemented circuit features the combination of four differential SCPAs through a four-way monolithic PC and is simulated to obtain a maximum drain efficiency of 44% at a peak output power of 29dBm on 1.1V supply voltage. Extensive spectrum analysis offers full evaluation of system performances. After exploring state-of-the-art possibilities offered by an advanced 28nm CMOS technology, this work predicts through rigorous theoretical analysis the expected evolution of SCPA performances with the scaling of CMOS Technologies. The encouraging forecast further emphasizes the importance of SCPA circuits for the future of high-performance Wireless Communications