102 research outputs found

    Efficient ASIC Architectures for Low Latency Niederreiter Decryption

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    Post-quantum cryptography addresses the increasing threat that quantum computing poses to modern communication systems. Among the available quantum-resistant systems, the Niederreiter cryptosystem is positioned as a conservative choice with strong security guarantees. As a code-based cryptosystem, the Niederreiter system enables high performance operations and is thus ideally suited for applications such as the acceleration of server workloads. However, until now, no ASIC architecture is available for low latency computation of Niederreiter operations. Therefore, the present work targets the design, implementation and optimization of tailored archi- tectures for low latency Niederreiter decryption. Two architectures utilizing different decoding algorithms are proposed and implemented using a 22nm FDSOI CMOS technology node. One of these optimized architectures improves the decryption latency by 27% compared to a state-of-the-art reference and requires at the same time only 25% of the area

    Optical Communication

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    Optical communication is very much useful in telecommunication systems, data processing and networking. It consists of a transmitter that encodes a message into an optical signal, a channel that carries the signal to its desired destination, and a receiver that reproduces the message from the received optical signal. It presents up to date results on communication systems, along with the explanations of their relevance, from leading researchers in this field. The chapters cover general concepts of optical communication, components, systems, networks, signal processing and MIMO systems. In recent years, optical components and other enhanced signal processing functions are also considered in depth for optical communications systems. The researcher has also concentrated on optical devices, networking, signal processing, and MIMO systems and other enhanced functions for optical communication. This book is targeted at research, development and design engineers from the teams in manufacturing industry, academia and telecommunication industries

    Hardware Architectures for Post-Quantum Cryptography

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    The rapid development of quantum computers poses severe threats to many commonly-used cryptographic algorithms that are embedded in different hardware devices to ensure the security and privacy of data and communication. Seeking for new solutions that are potentially resistant against attacks from quantum computers, a new research field called Post-Quantum Cryptography (PQC) has emerged, that is, cryptosystems deployed in classical computers conjectured to be secure against attacks utilizing large-scale quantum computers. In order to secure data during storage or communication, and many other applications in the future, this dissertation focuses on the design, implementation, and evaluation of efficient PQC schemes in hardware. Four PQC algorithms, each from a different family, are studied in this dissertation. The first hardware architecture presented in this dissertation is focused on the code-based scheme Classic McEliece. The research presented in this dissertation is the first that builds the hardware architecture for the Classic McEliece cryptosystem. This research successfully demonstrated that complex code-based PQC algorithm can be run efficiently on hardware. Furthermore, this dissertation shows that implementation of this scheme on hardware can be easily tuned to different configurations by implementing support for flexible choices of security parameters as well as configurable hardware performance parameters. The successful prototype of the Classic McEliece scheme on hardware increased confidence in this scheme, and helped Classic McEliece to get recognized as one of seven finalists in the third round of the NIST PQC standardization process. While Classic McEliece serves as a ready-to-use candidate for many high-end applications, PQC solutions are also needed for low-end embedded devices. Embedded devices play an important role in our daily life. Despite their typically constrained resources, these devices require strong security measures to protect them against cyber attacks. Towards securing this type of devices, the second research presented in this dissertation focuses on the hash-based digital signature scheme XMSS. This research is the first that explores and presents practical hardware based XMSS solution for low-end embedded devices. In the design of XMSS hardware, a heterogenous software-hardware co-design approach was adopted, which combined the flexibility of the soft core with the acceleration from the hard core. The practicability and efficiency of the XMSS software-hardware co-design is further demonstrated by providing a hardware prototype on an open-source RISC-V based System-on-a-Chip (SoC) platform. The third research direction covered in this dissertation focuses on lattice-based cryptography, which represents one of the most promising and popular alternatives to today\u27s widely adopted public key solutions. Prior research has presented hardware designs targeting the computing blocks that are necessary for the implementation of lattice-based systems. However, a recurrent issue in most existing designs is that these hardware designs are not fully scalable or parameterized, hence limited to specific cryptographic primitives and security parameter sets. The research presented in this dissertation is the first that develops hardware accelerators that are designed to be fully parameterized to support different lattice-based schemes and parameters. Further, these accelerators are utilized to realize the first software-harware co-design of provably-secure instances of qTESLA, which is a lattice-based digital signature scheme. This dissertation demonstrates that even demanding, provably-secure schemes can be realized efficiently with proper use of software-hardware co-design. The final research presented in this dissertation is focused on the isogeny-based scheme SIKE, which recently made it to the final round of the PQC standardization process. This research shows that hardware accelerators can be designed to offload compute-intensive elliptic curve and isogeny computations to hardware in a versatile fashion. These hardware accelerators are designed to be fully parameterized to support different security parameter sets of SIKE as well as flexible hardware configurations targeting different user applications. This research is the first that presents versatile hardware accelerators for SIKE that can be mapped efficiently to both FPGA and ASIC platforms. Based on these accelerators, an efficient software-hardwareco-design is constructed for speeding up SIKE. In the end, this dissertation demonstrates that, despite being embedded with expensive arithmetic, the isogeny-based SIKE scheme can be run efficiently by exploiting specialized hardware. These four research directions combined demonstrate the practicability of building efficient hardware architectures for complex PQC algorithms. The exploration of efficient PQC solutions for different hardware platforms will eventually help migrate high-end servers and low-end embedded devices towards the post-quantum era

    Pattern Recognition

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    A wealth of advanced pattern recognition algorithms are emerging from the interdiscipline between technologies of effective visual features and the human-brain cognition process. Effective visual features are made possible through the rapid developments in appropriate sensor equipments, novel filter designs, and viable information processing architectures. While the understanding of human-brain cognition process broadens the way in which the computer can perform pattern recognition tasks. The present book is intended to collect representative researches around the globe focusing on low-level vision, filter design, features and image descriptors, data mining and analysis, and biologically inspired algorithms. The 27 chapters coved in this book disclose recent advances and new ideas in promoting the techniques, technology and applications of pattern recognition

    Numerical modelling of additive manufacturing process for stainless steel tension testing samples

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    Nowadays additive manufacturing (AM) technologies including 3D printing grow rapidly and they are expected to replace conventional subtractive manufacturing technologies to some extents. During a selective laser melting (SLM) process as one of popular AM technologies for metals, large amount of heats is required to melt metal powders, and this leads to distortions and/or shrinkages of additively manufactured parts. It is useful to predict the 3D printed parts to control unwanted distortions and shrinkages before their 3D printing. This study develops a two-phase numerical modelling and simulation process of AM process for 17-4PH stainless steel and it considers the importance of post-processing and the need for calibration to achieve a high-quality printing at the end. By using this proposed AM modelling and simulation process, optimal process parameters, material properties, and topology can be obtained to ensure a part 3D printed successfully

    Area- Efficient VLSI Implementation of Serial-In Parallel-Out Multiplier Using Polynomial Representation in Finite Field GF(2m)

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    Finite field multiplier is mainly used in elliptic curve cryptography, error-correcting codes and signal processing. Finite field multiplier is regarded as the bottleneck arithmetic unit for such applications and it is the most complicated operation over finite field GF(2m) which requires a huge amount of logic resources. In this paper, a new modified serial-in parallel-out multiplication algorithm with interleaved modular reduction is suggested. The proposed method offers efficient area architecture as compared to proposed algorithms in the literature. The reduced finite field multiplier complexity is achieved by means of utilizing logic NAND gate in a particular architecture. The efficiency of the proposed architecture is evaluated based on criteria such as time (latency, critical path) and space (gate-latch number) complexity. A detailed comparative analysis indicates that, the proposed finite field multiplier based on logic NAND gate outperforms previously known resultsComment: 19 pages, 4 figure

    Regional Cerebral Blood Flow Patterns in Children vs. Adults with ADHD Combined and Inattentive Types: A SPECT Study

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    Objective: The current study sought to determine whether ADHD Combined Type (ADHD-C) and ADHD Primarily Inattentive Type (ADHD-PI) showed differential regional cerebral blood flow (rCBF) patterns in children vs. adults. Participants and Methods: The overall sample (N=1484) was effectively split into four groups: adults with ADHD-PI (n=519), adults with ADHD-C (n=405), children with ADHD-PI (n=192), children with ADHD-C (n=368). All participants were void of bipolar, schizophrenia, autism, neurocognitive disorders, and TBI. The data were collected from a de-identified archival database of individuals who underwent SPECT scans at rest. Results: Using αConclusions: Overall, the current study suggested that children may show rCBF differences between different ADHD subtypes, but adults may not. The current study did not find significance in any of the 17 brain regions examined when comparing adults with ADHD-C to adults with ADHD-PI. All significant findings were attributed to the children with ADHD-C group showing aberrant blood flow rate than at least one other group. Previous research has supported that the differentiation of these subtypes as distinctive disorders is difficult to make in adults (Sobanski et al., 2006). Other research has indicated the potential of imaging techniques to differentiate the two in children (Al-Amin, Zinchenko, & Geyer, 2018). The current findings support nuanced ways in which rCBF patterns of ADHD-C and ADHD-PI differ between children and adults

    The Effect of Ethnicity on Neuropsychological Test Performance of Former NFL Athletes

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    Objective: To investigate the effect of ethnicity on neuropsychological test performance by specifically exploring differences between white and black former NFL athletes on subtests of the WAIS-IV. Participants and Methods: Data was derived from a de-identified database in Florida consisting of 63 former NFL athletes (Mage=50.38; SD=11.57); 28 white and 35 black. Participants completed the following subtests of the WAIS-IV: Block Design, Similarities, Digit Span, Matrix Reasoning, Arithmetic, Symbol Search, Visual Puzzles, Coding, and Cancellation. Results: One-Way ANOVA yielded a significant effect between ethnicity and performance on several subtests. Black athletes had significantly lower scaled scores than white athletes on Block Design F(1,61)=14.266, p\u3c.001, Similarities F(1,61)=5.904, p=.018, Digit Span F(1,61)=8.985, p=.004, Arithmetic F(1,61)=16.07, p\u3c.001 and Visual Puzzles F(1,61)=16.682, p\u3c .001. No effect of ethnicity was seen on performance of Matrix Reasoning F(1,61)=2.937, p=.092, Symbol Search F(1,61)=3.619, p=.062, Coding F(1,61)=3.032, p=.087 or Cancellation F(1,61)=2.289, p=.136. Conclusions: Results reveal significant differences between white and black athletes on all subtests of the WAIS-IV but those from the Processing Speed Scale and Matrix Reasoning. These findings align with previous literature that found white individuals to outperform African-Americans on verbal and non-verbal tasks after controlling for socioeconomic and demographic variables (Manly & Jacobs, 2002). These differences may also be a reflection of the WAIS-IV’s psychometric properties and it is significant to consider the normative sample used may not be appropriate for African-Americans. This study highlights the need for future research to identify how ethnicity specifically influences performance, sheds light on the importance of considering cultural factors when interpreting test results, and serves as a call to action to further understand how and why minorities may not be accurately represented in neuropsychological testing

    Effects of Diversity and Neuropsychological Performance in an NFL Cohort

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    Objective: The aim of this study was to examine the effect of ethnicity on neuropsychological test performance by comparing scores of white and black former NFL athletes on each subtest of the WMS. Participants and Methods: Data was derived from a de-identified database in South Florida consisting of 63 former NFL white (n=28, 44.4%) and black (n=35, 55.6%) athletes (Mage= 50.38; SD= 11.57). Participants completed the following subtests of the WMS: Logical Memory I and II, Verbal Paired Associates I and II, and Visual Reproduction I and II. Results: A One-Way ANOVA yielded significant effect between ethnicity and performance on several subtests from the WMS-IV. Black athletes had significantly lower scores compared to white athletes on Logical Memory II: F(1,61) = 4.667, p= .035, Verbal Paired Associates I: F(1,61) = 4.536, p = .037, Verbal Paired Associates: II F(1,61) = 4.677, p = .034, and Visual Reproduction I: F(1,61) = 6.562, p = .013. Conclusions: Results suggest significant differences exist between white and black athletes on neuropsychological test performance, necessitating the need for proper normative samples for each ethnic group. It is possible the differences found can be explained by the psychometric properties of the assessment and possibility of a non-representative sample for minorities, or simply individual differences. Previous literature has found white individuals to outperform African-Americans on verbal and non-verbal cognitive tasks after controlling for socioeconomic and other demographic variables (Manly & Jacobs, 2002). This highlights the need for future investigators to identify cultural factors and evaluate how ethnicity specifically plays a role on neuropsychological test performance. Notably, differences between ethnic groups can have significant implications when evaluating a sample of former athletes for cognitive impairment, as these results suggest retired NFL minorities may be more impaired compared to retired NFL white athletes
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