A design methodology for integrated inductor-based DC-DC converters

A design methodology for monolithic integration of inductor based DC-DC converters is proposed in this paper. A power loss model of the power stage, including the drive circuits, is defined in order to optimize efficiency. Based on this model and taking as reference a 0.35 mu m CMOS process, a buck converter was designed and fabricated. For a given set of operating conditions the defined power loss model allows to optimize the design parameters for the power stage, including the gate-driver tapering factor and the width of the power MOSFETs. Experimental results obtained from a buck converter at 100 MHz switching frequency are presented to validate the proposed methodology

Design Methologies for Integrated Inductor-Based Soft-Switching DC DC Converters

This paper presents a study on resonant converter topologies targeted for CMOS integration. Design methodologies to optimize efficiency for the integration of Quasi-Resonant and Quasi-Square-Wave converters are proposed. A power loss model is used to optimize the design parameters of the power stage, including the driver circuits, and also to conclude about CMOS technology limitations. Based on this discussion, and taking as reference a 0.35μm CMOS process, two converters are designed to validate the proposal: a Quasi Resonant boost converter operating at 100MHz and a Quasi-Square-Wave buck converter operating at 70MHz. Simulation results confirm the feasibility of these topologies for monolithic integration