Bio-inspired 0.35μm CMOS Time-to-Digital Converter with 29.3ps LSB

Time-to-digital converter (TDC) integrated circuit is introduced in this paper. It is based on chain of delay elements composing a regular scalable structure. The scheme is analogous to the sound direction sensitivity nerve system found in barn owl. The circuit occupies small silicon area, and its direct mapping from time to position-code makes conversion rates up to 500Msps possible. Specialty of the circuit is the structural and functional symmetry. Therefore the role of start and stop signals are interchangeable. In other words negative delay is acceptable: the circuit has no dead time problems. These are benefits of the biology model of the auditory scene representation in the bird's brain. The prototype chip is implemented in 0.35μm CMOS having less than 30ps single-shot resolution in the measurements.Hungarian National Research Foundation TS4085

Optimal Positions of Twists in Global On-Chip Differential Interconnects

Crosstalk limits the achievable data rate of global on-chip interconnects on large CMOS ICs. This is especially the case, if low-swing signaling is used to reduce power consumption. Differential interconnects provide a solution for most crosstalk and noise sources, but not for neighbor-to-neighbor crosstalk in a data bus. This neighbor-to-neighbor crosstalk can be reduced with twists in the differential interconnect pairs. To reduce via resistance and metal layer use, we use as few twists as possible by placing only one twist in every even interconnect pair and only two twists in every odd interconnect pair. Analysis shows that there are optimal positions for the twists, which depend on the termination impedances of the interconnects. Theory and measurements on a 10-mm-long bus in 0.13-mum CMOS show that only one twist at 50% of the even interconnect pairs, two twists at 30% and 70% of the odd interconnect pairs, and both a low-ohmic source and a low-ohmic load impedance are very effective in mitigating the crosstal

Variation Resilient Adaptive Controller for Subthreshold Circuits

Subthreshold logic is showing good promise as a viable ultra-low-power circuit design technique for power-limited applications. For this design technique to gain widespread adoption, one of the most pressing concerns is how to improve the robustness of subthreshold logic to process and temperature variations. We propose a variation resilient adaptive controller for subthreshold circuits with the following novel features: new sensor based on time-to-digital converter for capturing the variations accurately as digital signatures, and an all-digital DC-DC converter incorporating the sensor capable of generating an operating operating Vdd from 0V to 1.2V with a resolution of 18.75mV, suitable for subthreshold circuit operation. The benefits of the proposed controller is reflected with energy improvement of up to 55% compared to when no controller is employed. The detailed implementation and validation of the proposed controller is discussed

Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review

The technological evolution has increased the number of transistors for a given die area significantly and increased the switching speed from few MHz to GHz range. Such inversely proportional decline in size and boost in performance consequently demands shrinking of supply voltage and effective power dissipation in chips with millions of transistors. This has triggered substantial amount of research in power reduction techniques into almost every aspect of the chip and particularly the processor cores contained in the chip. This paper presents an overview of techniques for achieving the power efficiency mainly at the processor core level but also visits related domains such as buses and memories. There are various processor parameters and features such as supply voltage, clock frequency, cache and pipelining which can be optimized to reduce the power consumption of the processor. This paper discusses various ways in which these parameters can be optimized. Also, emerging power efficient processor architectures are overviewed and research activities are discussed which should help reader identify how these factors in a processor contribute to power consumption. Some of these concepts have been already established whereas others are still active research areas. © 2009 ACADEMY PUBLISHER

Generic tests of the existence of the gravitational dipole radiation and the variation of the gravitational constant

We present results from the high precision timing analysis of the pulsar-white dwarf (WD) binary PSR J1012+5307 using 15 years of multi-telescope data. Observations were performed regularly by the European Pulsar Timing Array (EPTA) network, consisting of Effelsberg, Jodrell Bank, Westerbork and Nan\c{c}ay. All the timing parameters have been improved from the previously published values, most by an order of magnitude. In addition, a parallax measurement of $\pi = 1.2(3)$ mas is obtained for the first time for PSR J1012+5307, being consistent with the optical estimation from the WD companion. Combining improved 3D velocity information and models for the Galactic potential the complete evolutionary Galactic path of the system is obtained. A new intrinsic eccentricity upper limit of $e<8.4\times 10^{-7}$ is acquired, one of the smallest calculated for a binary system and a measurement of the variation of the projected semi-major axis also constrains the system's orbital orientation for the first time. It is shown that PSR J1012+5307 is an ideal laboratory for testing alternative theories of gravity. The measurement of the change of the orbital period of the system of $\dot{P}_{b} = 5(1)\times 10^{-14}$ is used to set an upper limit on the dipole gravitational wave emission that is valid for a wide class of alternative theories of gravity. Moreover, it is shown that in combination with other binary pulsars PSR J1012+5307 is an ideal system to provide self-consistent, generic limits, based only on millisecond pulsar data, for the dipole radiation and the variation of the gravitational constant $\dot{G}$.Comment: accepted for publication in MNRAS, 11 pages, 5 figures, 2 table