1 research outputs found
Ratatoskr: An open-source framework for in-depth power, performance and area analysis in 3D NoCs
We introduce ratatoskr, an open-source framework for in-depth power,
performance and area (PPA) analysis in NoCs for 3D-integrated and heterogeneous
System-on-Chips (SoCs). It covers all layers of abstraction by providing a NoC
hardware implementation on RT level, a NoC simulator on cycle-accurate level
and an application model on transaction level. By this comprehensive approach,
ratatoskr can provide the following specific PPA analyses: Dynamic power of
links can be measured within 2.4% accuracy of bit-level simulations while
maintaining cycle-accurate simulation speed. Router power is determined from RT
level synthesis combined with cycle-accurate simulations. The performance of
the whole NoC can be measured both via cycle-accurate and RT level simulations.
The performance of individual routers is obtained from RT level including
gate-level verification. The NoC area is calculated from RT level. Despite
these manifold features, ratatoskr offers easy two-step user interaction:
First, a single point-of-entry that allows to set design parameters and second,
PPA reports are generated automatically. For both the input and the output,
different levels of abstraction can be chosen for high-level rapid network
analysis or low-level improvement of architectural details. The synthesize NoC
model reduces up to 32% total router power and 3% router area in comparison to
a conventional standard router. As a forward-thinking and unique feature not
found in other NoC PPA-measurement tools, ratatoskr supports heterogeneous 3D
integration that is one of the most promising integration paradigms for
upcoming SoCs. Thereby, ratatoskr lies the groundwork to design their
communication architectures