Design of a Class-D RF power amplifier in CMOS technology

In this thesis an RF Class-D Power Amplifier is presented. The analysis of the Class-D amplifier considering ideal components has shown that the drain efficiency of 100% can be achieved. The output power and the drain efficiency are degraded by the internal resistance of each component. A driver is used to drive the gate capacitances of the Class-D amplifier. Both driver and amplifier are implemented with CMOS inverters. The size of the inverters in the driver is scaled down by a factor of 3 relatively to the preceding stage. The first being the inverter of the Class-D amplifier. At the output a 3rd order Butterworth bandpass filter is implemented. A non-ideal analysis of the Class-D amplifier is performed to create a base model which is used to aid in the design of the circuit. The RF Class-D Power Amplifier with the operation frequency of 2.4GHz was implemented with standard 130 nm CMOS technology. Two simulations were taken into account considering ideal and pre-layout components in the output filter. The following results were obtained when using ideal components: the output power of 6.91 dBm, the drain efficiency of 40% and the overall efficiency of 23%. Using pre-layout components the results were the following: the output power of 0.317 dBm the drain and overall efficiency of 8.6% and 4.9%, respectively

High-efficiency, wideband RF power amplifiers for cellular infrastructure

Over the past decade, the exponential increase in demand for data content has led to many challenges for the cellular networks. More spectrally efficient modulation formats place tight linearity requirements on the system, and the high peak to average ratio of the signals requires the use of power amplifier architectures with high efficiency at backed-off power levels. Also, the push toward multi-band radios demands the use of wideband power amplifiers in the place of multiple single band amplifiers. This work focuses on the following areas of research:- RF Bandwidth Much research focuses on achieving wideband solutions at low frequency (sub 1GHz) or low power (<20W) through the absorption of device parasitics into the matching structures. This work focuses on Doherty amplifier topologies with bandwidths (up to 40% fractional) and power levels (over 100 watts) appropriate for cellular infrastructure applications. The bandwidth of each element in the Doherty amplifier is analyzed across frequency when load modulated. Several novel wideband Doherty amplifier topologies are presented, and two demonstration amplifiers are designed, achieving the state of the art performance. Linearity In recent years, there has been considerable research focus to enhance the linearity of the RF power amplifier when linearized in a digital pre-distortion (DPD) system. Much of this research focuses on the output baseband impedance of the device and circuit. However, until very recently, little work focused on the impact of the device input. This research focuses on the effects of the input baseband impedance of the device and circuit, with a novel input matching topology Abstract III proposed to enable virtually ideal impedance characteristics. A novel integrated passive device is developed to enable the proposed topology, and the enhanced DPD correction, when compared to the current state of the art, is demonstrated using a 60-watt LDMOS device. Performance Scaling with Power and Frequency This research focuses on the minimization of performance impact due to device power scaling at high frequency. A proposed waveform engineering analysis and optimization method using 3D electromagnetic simulation with load-pull is proposed. In addition, a novel matching topology using multi-level, high Q integrated passive devices (IPD) is proposed. The analysis method is used to demonstrate a reduced performance degradation through enhanced voltage and current waveform uniformity across the power transistor. For the first time, the concept of active harmonic impedances due to the distributed effects of a high power RF device is presented

Multi-Loop-Ring-Oscillator Design and Analysis for Sub-Micron CMOS

Ring oscillators provide a central role in timing circuits for today?s mobile devices and desktop computers. Increased integration in these devices exacerbates switching noise on the supply, necessitating improved supply resilience. Furthermore, reduced voltage headroom in submicron technologies limits the number of stacked transistors available in a delay cell. Hence, conventional single-loop oscillators offer relatively few design options to achieve desired specifications, such as supply rejection. Existing state-of-the-art supply-rejection- enhancement methods include actively regulating the supply with an LDO, employing a fully differential or current-starved delay cell, using a hi-Z voltage-to-current converter, or compensating/calibrating the delay cell. Multiloop ring oscillators (MROs) offer an additional solution because by employing a more complex ring-connection structure and associated delay cell, the designer obtains an additional degree of freedom to meet the desired specifications. Designing these more complex multiloop structures to start reliably and achieve the desired performance requires a systematic analysis procedure, which we attack on two fronts: (1) a generalized delay-cell viewpoint of the MRO structure to assist in both analysis and circuit layout, and (2) a survey of phase-noise analysis to provide a bank of methods to analyze MRO phase noise. We distill the salient phase-noise-analysis concepts/key equations previously developed to facilitate MRO and other non-conventional oscillator analysis. Furthermore, our proposed analysis framework demonstrates that all these methods boil down to obtaining three things: (1) noise modulation function (NMF), (2) noise transfer function (NTF), and (3) current-controlled-oscillator gain (KICO). As a case study, we detail the design, analysis, and measurement of a proposed multiloop ring oscillator structure that provides improved power-supply isolation (more than 20dB increase in supply rejection over a conventional-oscillator control case fabricated on the same test chip). Applying our general multi-loop-oscillator framework to this proposed MRO circuit leads both to design-oriented expressions for the oscillation frequency and supply rejection as well as to an efficient layout technique facilitating cross-coupling for improved quadrature accuracy and systematic, substantially simplified layout effort

Multi-Loop-Ring-Oscillator Design and Analysis for Sub-Micron CMOS

Ring oscillators provide a central role in timing circuits for today?s mobile devices and desktop computers. Increased integration in these devices exacerbates switching noise on the supply, necessitating improved supply resilience. Furthermore, reduced voltage headroom in submicron technologies limits the number of stacked transistors available in a delay cell. Hence, conventional single-loop oscillators offer relatively few design options to achieve desired specifications, such as supply rejection. Existing state-of-the-art supply-rejection- enhancement methods include actively regulating the supply with an LDO, employing a fully differential or current-starved delay cell, using a hi-Z voltage-to-current converter, or compensating/calibrating the delay cell. Multiloop ring oscillators (MROs) offer an additional solution because by employing a more complex ring-connection structure and associated delay cell, the designer obtains an additional degree of freedom to meet the desired specifications. Designing these more complex multiloop structures to start reliably and achieve the desired performance requires a systematic analysis procedure, which we attack on two fronts: (1) a generalized delay-cell viewpoint of the MRO structure to assist in both analysis and circuit layout, and (2) a survey of phase-noise analysis to provide a bank of methods to analyze MRO phase noise. We distill the salient phase-noise-analysis concepts/key equations previously developed to facilitate MRO and other non-conventional oscillator analysis. Furthermore, our proposed analysis framework demonstrates that all these methods boil down to obtaining three things: (1) noise modulation function (NMF), (2) noise transfer function (NTF), and (3) current-controlled-oscillator gain (KICO). As a case study, we detail the design, analysis, and measurement of a proposed multiloop ring oscillator structure that provides improved power-supply isolation (more than 20dB increase in supply rejection over a conventional-oscillator control case fabricated on the same test chip). Applying our general multi-loop-oscillator framework to this proposed MRO circuit leads both to design-oriented expressions for the oscillation frequency and supply rejection as well as to an efficient layout technique facilitating cross-coupling for improved quadrature accuracy and systematic, substantially simplified layout effort

Power Converters in Power Electronics

In recent years, power converters have played an important role in power electronics technology for different applications, such as renewable energy systems, electric vehicles, pulsed power generation, and biomedical sciences. Power converters, in the realm of power electronics, are becoming essential for generating electrical power energy in various ways. This Special Issue focuses on the development of novel power converter topologies in power electronics. The topics of interest include, but are not limited to: Z-source converters; multilevel power converter topologies; switched-capacitor-based power converters; power converters for battery management systems; power converters in wireless power transfer techniques; the reliability of power conversion systems; and modulation techniques for advanced power converters

Design and Control of Power Converters 2020

In this book, nine papers focusing on different fields of power electronics are gathered, all of which are in line with the present trends in research and industry. Given the generality of the Special Issue, the covered topics range from electrothermal models and losses models in semiconductors and magnetics to converters used in high-power applications. In this last case, the papers address specific problems such as the distortion due to zero-current detection or fault investigation using the fast Fourier transform, all being focused on analyzing the topologies of high-power high-density applications, such as the dual active bridge or the H-bridge multilevel inverter. All the papers provide enough insight in the analyzed issues to be used as the starting point of any research. Experimental or simulation results are presented to validate and help with the understanding of the proposed ideas. To summarize, this book will help the reader to solve specific problems in industrial equipment or to increase their knowledge in specific fields

Techniques for high-efficiency outphasing power amplifiers

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.Cataloged from PDF version of thesis.Includes bibliographical references (p. 171-177).A trade-off between linearity and efficiency exists in conventional power amplifiers (PAs). The outphase amplifying concept overcomes this trade-off by enabling the use of high efficiency, non-linear power amplifiers for linear amplification. However, the efficiency improvement is limited by the efficiency of the output power combiner. This thesis investigates techniques to overcome this efficiency limit while maintaining sufficient linearity. Two techniques are proposed. The first technique is called the outphasing energy recovery amplifier (OPERA), which recovers the normally wasted power back to the power supply and utilizes a resistance compression network for improved linearity. A 48-MHz, 20-W prototype OPERA system was built which demonstrates more than 2x higher efficiency than the standard outphasing system for a 16-QAM signal. The second technique to improve the efficiency of the outphasing system is asymmetric multilevel outphasing (AMO) modulation. In the AMO system, the amplitude for each of the two outphased PAs can switch independently among multiple discrete levels, significantly reducing the energy lost in the power combiner. Three different AMO prototypes were built, each of which demonstrate between 2x-3x efficiency improvement compared to the standard outphasing system. A 2.4-GHz, 500- mW prototype made in a 65-nm CMOS process achieves an average system efficiency of 28.7% for a 20-MHz 64-QAM signal. To the author's best knowledge, this is the highest reported efficiency for a CMOS PA in the 2-2.7 GHz range for signal bandwidths greater than 10 MHz.by Philip Andrew Godoy.Ph.D

Ultra-Low-Power Sensors and Receivers for IoT Applications

The combination of ultra-low power analog front-ends and CMOS-compatible transducers enable new applications, such as environmental monitors, household appliances, health trackers, etc. that are seamlessly integrated into our daily lives. Furthermore, wireless connectivity allows many of these sensors to operate both independently and collectively. These techniques collectively fulfil the recent surge of internet-of-things (IoT) applications that have the potential to fundamentally change daily life for millions of people.In this dissertation, the circuit and system design of wireless receivers and sensors is presented that explores the challenges of implementing long lifespan, high accuracy, and large coverage range IoT sensor networks. The first is a wake-up receiver (WuRX), which continuously monitors the RF environment to wake up a higher-power radio upon detection of a predetermined RF signature. This work both improves sensitivity and reduces power over prior art through a multi-faceted design featuring an impedance transformation network with large passive voltage gain, an active envelope detector with high input impedance to facilitate large passive voltage gain, a low-power precision comparator, and a low-leakage digital baseband correlator.Although pushing the prior WuRX performance boundary by orders of magnitude, the first work shows moderate sensitivity, inferior temperature robustness, and large area with external lumped components. Thus, the second work shows a miniaturized WuRX that is temperature-compensated, yet still consumes only nano-watt power and millimeter area while operating at 9 GHz. To further reduce the area, a global common-mode feedback is utilized across the envelope detector and baseband amplifier that eliminates the need for off-chip ac-coupling components. Multiple temperature-compensation techniques are proposed to maintain constant bandwidth of the signal path and constant clock frequency. Both WuRXs operate at 0.4 V supply, consume near-zero power and achieve ~-70 dBm sensitivity.Lastly, the first reported CMOS 2-in-1 relative humidity and temperature sensor is presented. A unified analog front-end interfaces on-chip transducers and converts the inputs into a frequency vis a high-linearity frequency-locked loop. An incomplete-settling switched-capacitor-based Wheatstone bridge is proposed to sense the inputs in a power-efficient fashion