Time interleaved counter analog to digital converters

The work explores extending time interleaving in A/D converters, by applying a high-level of parallelism to one of the slowest and simplest types of data-converters, the counter ADC. The motivation for the work is to realise high-performance re-configurable A/D converters for use in multi-standard and multi-PHY communication receivers with signal bandwidths in the 10s to 100s of MHz. The counter ADC requires only a comparator, a ramp signal, and a digital counter, where the comparator compares the sampled input against all possible quantisation levels sequentially. This work explores arranging counter ADCs in large time-interleaved arrays, building a Time Interleaved Counter (TIC) ADC. The key to realising a TIC ADC is distributed sampling and a global multi-phase ramp generator realised with a novel figure-of-8 rotating resistor ring. Furthermore Counter ADCs allow for re-configurability between effective sampling rate and resolution due to their sequential comparison of reference levels in conversion. A prototype TIC ADC of 128-channels was fabricated and measured in 0.13μm CMOS technology, where the same block can be configured to operate as a 7-bit 1GS/s, 8-bit 500MS/s, or 9-bit 250MS/s dataconverter. The ADC achieves a sub 400fJ/step FOM in all modes of configuration

Design of a Time-of-Flight Sensor with Standard Pinned-Photodiode Devices Towards 100 MHz Modulation Frequency

We present an indirect Time-of-Flight (ToF) sensor based on standard pinned-photodiode (PPD) devices and design guides to pave the way for the development of a ToF pixel operating at 100 MHz modulation frequency. The standard PPDs are established well as predominant devices for 2-D color imagers in these days because of their low noise characteristic, but slow transfer speed of photo-generated electrons still prevents them from being employed to 3-D depth imagers. Optimized PPD structure with no process modifications is introduced to create a lateral electric field for enhancing charge transfer speed inside the PPD, and essential design parameters for achieving high operating frequency such as the epitaxial layer thickness, the pinning voltage, and the threshold voltage of the transfer gates are discussed with TCAD simulation results in this paper. Prototype indirect ToF sensors with various structures and parameters were fabricated using a 0.11-??m standard CIS process and characterized fully. We successfully evaluated the demodulation contrast of each pixel at 10 to 75 MHz frequencies, figuring out the suitable conditions of the PPD-based pixel. The best pixel operating at 50 MHz frequency demonstrated a depth resolution of less than 13 mm and a linearity error of about 3.7% between 1 and 3 m distance with a zeroorder calibration. We believe further optimization of the ToF pixel incorporated with the PPD devices is possible to improve the performance, operating it towards 100 MHz modulation frequency

High-Speed Wide-Field Time-Correlated Single-Photon Counting Fluorescence Lifetime Imaging Microscopy

Fluorescence microscopy is a powerful imaging technique used in the biological sciences to identify labeled components of a sample with specificity. This is usually accomplished through labeling with fluorescent dyes, isolating these dyes by their spectral signatures with optical filters, and recording the intensity of the fluorescent response. Although these techniques are widely used, fluorescence intensity images can be negatively affected by a variety of factors that impact the fluorescence intensity. Fluorescence lifetime imaging microscopy (FLIM) is an imaging technique that is relatively immune to intensity fluctuations and also provides the unique ability to directly monitor the microenvironment surrounding a fluorophore. Despite the benefits associated with FLIM, the applications to which it is applied are fairly limited due to long image acquisition times and high cost of traditional hardware. Recent advances in complementary metal-oxide-semiconductor (CMOS) single-photon avalanche diodes (SPADs) have enabled the design of low-cost imaging arrays that are capable of recording lifetime images with acquisition times greater than one order of magnitude faster than existing systems. However, these SPAD arrays have yet to realize the full potential of the technology due to limitations in their ability to handle the vast amount of data generated during the commonly used time-correlated single-photon counting (TCSPC) lifetime imaging technique. This thesis presents the design, implementation, characterization, and demonstration of a high speed FLIM imaging system. The components of this design include a CMOS imager chip in a standard 0.13 μm technology containing a custom CMOS SPAD, a 64-by-64 array of these SPADs, pixel control circuitry, independent time-to-digital converters (TDCs), a FLIM specific datapath, and high bandwidth output buffers. In addition to the CMOS imaging array, a complete system was designed and implemented using a printed circuit board (PCB) for capturing data from the imager, creating histograms for the photon arrival data using field-programmable gate arrays, and transferring the data to a computer using a cabled PCIe interface. Finally, software is used to communicate between the imaging system and a computer.The dark count rate of the SPAD was measured to be only 231 Hz at room temperature while maintaining a photon detection probability of up to 30\%. TDCs included on the array have a 62.5 ps resolution and a 64 ns range, which is suitable for measuring the lifetime of most biological fluorophores. Additionally, the on-chip datapath was designed to handle continuous data transfers at rates capable of supporting TCSPC-based lifetime imaging at 100 frames per second. The system level implementation also provides sufficient data throughput for transferring up to 750 frames per second from the imaging system to a computer. The lifetime imaging system was characterized using standard techniques for evaluating SPAD performance and an electrical delay signal for measuring the TDC performance. This thesis concludes with a demonstration of TCSPC-FLIM imaging at 100 frames per second -- the fastest 64-by-64 TCSPC FLIM that has been demonstrated. This system overcomes some of the limitations of existing FLIM systems and has the potential to enable new application domains in dynamic FLIM imaging

Challenges and Solutions to Next-Generation Single-Photon Imagers

Detecting and counting single photons is useful in an increasingly large number of applications. Most applications require large formats, approaching and even far exceeding 1 megapixel. In this thesis, we look at the challenges of massively parallel photon-counting cameras from all performance angles. The thesis deals with a number of performance issues that emerge when the number of pixels exceeds about 1/4 of megapixels, proposing characterization techniques and solutions to mitigate performance degradation and non-uniformity. Two cameras were created to validate the proposed techniques. The first camera, SwissSPAD, comprises an array of 512 x 128 SPAD pixels, each with a one-bit memory and a gating mechanism to achieve 5ns high precision time windows with high uniformity across the array. With a massively parallel readout of over 10 Gigabit/s and positioning of the integration time window accurate to the pico-second range, fluorescence lifetime imaging and fluorescence correlation spectroscopy imaging achieve a speedup of several orders of magnitude while ensuring high precision in the measurements. Other possible applications include wide-field time-of-flight imaging and the generation of quantum random numbers at highest bit-rates. Lately super-resolution microscopy techniques have also used SwissSPAD. The second camera, LinoSPAD, takes the concepts of SwissSPAD one step further by moving even more 'intelligence' to the FPGA and reducing the sensor complexity to the bare minimum. This allows focusing the optimization of the sensor on the most important metrics of photon efficiency and fill factor. As such, the sensor consists of one line of SPADs that have a direct connection each to the FPGA where complex photon processing algorithms can be implemented. As a demonstration of the capabilities of current lowcost FPGAs we implemented an array of time-to-digital converters that can handle up to 8.5 billion photons per second, measuring each one of them and accounting them in high precision histograms. Using simple laser diodes and a circuit to generate light pulses in the picosecond range, we demonstrate a ubiquitous 3D time-of-flight sensor. The thesis intends to be a first step towards achieving the world's first megapixel SPAD camera, which, we believe, is in grasp thanks to the architectural and circuital techniques proposed in this thesis. In addition, we believe that the applications proposed in this thesis offer a wide variety of uses of the sensors presented in this thesis and in future ones to come

A portable device for time-resolved fluorescence based on an array of CMOS SPADs with integrated microfluidics

[eng] Traditionally, molecular analysis is performed in laboratories equipped with desktop instruments operated by specialized technicians. This paradigm has been changing in recent decades, as biosensor technology has become as accurate as desktop instruments, providing results in much shorter periods and miniaturizing the instrumentation, moving the diagnostic tests gradually out of the central laboratory. However, despite the inherent advantages of time-resolved fluorescence spectroscopy applied to molecular diagnosis, it is only in the last decade that POC (Point Of Care) devices have begun to be developed based on the detection of fluorescence, due to the challenge of developing high-performance, portable and low-cost spectroscopic sensors. This thesis presents the development of a compact, robust and low-cost system for molecular diagnosis based on time-resolved fluorescence spectroscopy, which serves as a general-purpose platform for the optical detection of a variety of biomarkers, bridging the gap between the laboratory and the POC of the fluorescence lifetime based bioassays. In particular, two systems with different levels of integration have been developed that combine a one-dimensional array of SPAD (Single-Photon Avalanch Diode) pixels capable of detecting a single photon, with an interchangeable microfluidic cartridge used to insert the sample and a laser diode Pulsed low-cost UV as a source of excitation. The contact-oriented design of the binomial formed by the sensor and the microfluidic, together with the timed operation of the sensors, makes it possible to dispense with the use of lenses and filters. In turn, custom packaging of the sensor chip allows the microfluidic cartridge to be positioned directly on the sensor array without any alignment procedure. Both systems have been validated, determining the decomposition time of quantum dots in 20 nl of solution for different concentrations, emulating a molecular test in a POC device.[cat] Tradicionalment, l'anàlisi molecular es realitza en laboratoris equipats amb instruments de sobretaula operats per tècnics especialitzats. Aquest paradigma ha anat canviant en les últimes dècades, a mesura que la tecnologia de biosensor s'ha tornat tan precisa com els instruments de sobretaula, proporcionant resultats en períodes molt més curts de temps i miniaturitzant la instrumentació, permetent així, traslladar gradualment les proves de diagnòstic fora de laboratori central. No obstant això i malgrat els avantatges inherents de l'espectroscòpia de fluorescència resolta en el temps aplicada a la diagnosi molecular, no ha estat fins a l'última dècada que s'han començat a desenvolupar dispositius POC (Point Of Care) basats en la detecció de la fluorescència, degut al desafiament que suposa el desenvolupament de sensors espectroscòpics d'alt rendiment, portàtils i de baix cost. Aquesta tesi presenta el desenvolupament d'un sistema compacte, robust i de baix cost per al diagnòstic molecular basat en l'espectroscòpia de fluorescència resolta en el temps, que serveixi com a plataforma d'ús general per a la detecció òptica d'una varietat de biomarcadors, tancant la bretxa entre el laboratori i el POC dels bioassaigs basats en l'anàlisi de la pèrdua de la fluorescència. En particular, s'han desenvolupat dos sistemes amb diferents nivells d'integració que combinen una matriu unidimensional de píxels SPAD (Single-Photon Avalanch Diode) capaços de detectar un sol fotó, amb un cartutx microfluídic intercanviable emprat per inserir la mostra, així com un díode làser UV premut de baix cost com a font d'excitació. El disseny orientat a la detecció per contacte de l'binomi format pel sensor i la microfluídica, juntament amb l'operació temporitzada dels sensors, permet prescindir de l'ús de lents i filtres. Al seu torn, l'empaquetat a mida de l'xip sensor permet posicionar el cartutx microfluídic directament sobre la matriu de sensors sense cap procediment d'alineament. Tots dos sistemes han estat validats determinant el temps de descomposició de "quantum dots" en 20 nl de solució per a diferents concentracions, emulant així un assaig molecular en un dispositiu POC

Miniature high dynamic range time-resolved CMOS SPAD image sensors

Since their integration in complementary metal oxide (CMOS) semiconductor technology in 2003, single photon avalanche diodes (SPADs) have inspired a new era of low cost high integration quantum-level image sensors. Their unique feature of discerning single photon detections, their ability to retain temporal information on every collected photon and their amenability to high speed image sensor architectures makes them prime candidates for low light and time-resolved applications. From the biomedical field of fluorescence lifetime imaging microscopy (FLIM) to extreme physical phenomena such as quantum entanglement, all the way to time of flight (ToF) consumer applications such as gesture recognition and more recently automotive light detection and ranging (LIDAR), huge steps in detector and sensor architectures have been made to address the design challenges of pixel sensitivity and functionality trade-off, scalability and handling of large data rates. The goal of this research is to explore the hypothesis that given the state of the art CMOS nodes and fabrication technologies, it is possible to design miniature SPAD image sensors for time-resolved applications with a small pixel pitch while maintaining both sensitivity and built -in functionality. Three key approaches are pursued to that purpose: leveraging the innate area reduction of logic gates and finer design rules of advanced CMOS nodes to balance the pixel’s fill factor and processing capability, smarter pixel designs with configurable functionality and novel system architectures that lift the processing burden off the pixel array and mediate data flow. Two pathfinder SPAD image sensors were designed and fabricated: a 96 × 40 planar front side illuminated (FSI) sensor with 66% fill factor at 8.25μm pixel pitch in an industrialised 40nm process and a 128 × 120 3D-stacked backside illuminated (BSI) sensor with 45% fill factor at 7.83μm pixel pitch. Both designs rely on a digital, configurable, 12-bit ripple counter pixel allowing for time-gated shot noise limited photon counting. The FSI sensor was operated as a quanta image sensor (QIS) achieving an extended dynamic range in excess of 100dB, utilising triple exposure windows and in-pixel data compression which reduces data rates by a factor of 3.75×. The stacked sensor is the first demonstration of a wafer scale SPAD imaging array with a 1-to-1 hybrid bond connection. Characterisation results of the detector and sensor performance are presented. Two other time-resolved 3D-stacked BSI SPAD image sensor architectures are proposed. The first is a fully integrated 5-wire interface system on chip (SoC), with built-in power management and off-focal plane data processing and storage for high dynamic range as well as autonomous video rate operation. Preliminary images and bring-up results of the fabricated 2mm² sensor are shown. The second is a highly configurable design capable of simultaneous multi-bit oversampled imaging and programmable region of interest (ROI) time correlated single photon counting (TCSPC) with on-chip histogram generation. The 6.48μm pitch array has been submitted for fabrication. In-depth design details of both architectures are discussed

Électronique d’un convertisseur photon-numérique 3D pour une résolution temporelle de 10 ps FWHM

Les technologies utilisant la détection monophotonique sont de plus en plus présentes dans nos vies. De nombreuses applications nécessitent un photodétecteur possédant une haute efficacité de détection ainsi que d’excellentes performances temporelles, de l’ordre de 10 ps LMH. L’un des exemples qui aura un impact dans nos vies à court terme est l’intégration de système de télémétrie laser sur les véhicules afin de les rendre autonomes. Le domaine de l’imagerie médicale peut également profiter du développement de nouveaux photodétecteurs possédant une très haute précision temporelle. Par exemple, la tomographie d’émission par positrons permet d’imager le métabolisme des cellules, une technique très utilisée dans la détection de tumeurs cancéreuses. Une résolution temporelle en coïncidence de 10 ps LMH permet d’augmenter drastiquement le contraste des images des scanners TEP en localisant l’endroit sur la ligne de réponse où s’est produite l’annihilation du positron et de l’électron. L’atteinte d’une résolution de 10 ps LMH représenterait un changement de paradigme puisqu’il serait possible de produire directement une image sans utiliser un processus de reconstruction. Présentement, les cristaux scintillateurs et les photodétecteurs sont les deux facteurs limitant l’atteinte d’une résolution de 10 ps LMH. Au niveau du photodétecteur, une gigue temporelle de détection de photon unique de 10 ps LMH est requise pour atteindre une résolution en coïncidence de 10 ps LMH. Le Groupe de recherche en appareillage médicale travaille à atteindre cette performance depuis de nombreuses années. Le projet phare du groupe au niveau du développement de photodétecteur est le convertisseur photon-numérique 3D. Pour ce détecteur, une intégration verticale 3D de deux puces de silicium est requise. Sur la première couche, une matrice de photodiode à avalanche monophotonique est conçue dans une technologie sur mesure de Teledyne Dalsa Semiconductor Inc est intégrée en 3D sur une seconde couche de technologie standard CMOS 65 nm de Taiwan Semiconductor Manufacturing Company ltd. Ce projet de doctorat vise à concevoir un circuit en technologie CMOS qui attribue à chaque photodiode à avalanche monophotonique un circuit d’étouffement et un convertisseur temps-numérique possédant une gigue sous les 10 ps LMH. Cette thèse présente le développement d’une matrice de 256 circuits de lecture de photodiodes à avalanche monophotonique optimisés pour obtenir la meilleure résolution temporelle tout en intégrant un circuit de traitement numérique. Pour atteindre une résolution de 10 ps LMH, un système de correction des non-uniformités et des variations de délai de propagation de chaque pixel a été implémenté. Pour finir, cette recherche conclut sur l’implémentation d’un circuit d’asservissement pour stabiliser les performances du convertisseur temps-numérique pour les variations de tension d’alimentations et de température

TIME-DIFFERENCE CIRCUITS: METHODOLOGY, DESIGN, AND DIGITAL REALIZATION

This thesis presents innovations for a special class of circuits called Time Difference (TD) circuits. We introduce a signal processing methodology with TD signals that alters the target signal from a magnitude perspective to time interval between two time events and systematically organizes the primary TD functions abstracted from existing TD circuits and systems. The TD circuits draw attention from a broad range of application fields. In addition, highly evolved complementary metal-oxide-semiconductor (CMOS) technology suffers from various problems related to voltage and current amplitude signal processing methods. Compared to traditional analog and digital circuits, TD circuits bring several compelling features: high-resolution, high-throughput, and low-design complexity with digital integration capability. Further, the fabrication technology is advancing into the nanometer regime; the reduction in voltage headroom limits the performance of traditional analog/mixed-signal designs. All-digital design of time-difference circuit needs to be stressed to adapt to the low-cost, low-power, and high-portability applications. We focus on Time-to-Digital Converters (TDC), one of the crucial building blocks in TD circuits. A novel algorithmic architecture is proposed based on a binary search algorithm and validated with both simulation and fabricated silicon. An all-digital structure Time-difference Amplifier (TDA) is designed and implemented to make FPGA and other all-digital implementations for TDC and related TD circuits feasible. Besides, we propose an all-digital timing measurement circuit based on the process variation from CMOS fabrication: PVTMC, which achieves a high measurement resolution:

Design and debugging of multi-step analog to digital converters

With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. The trend of increasing integration level for integrated circuits has forced the A/D converter interface to reside on the same silicon in complex mixed-signal ICs containing mostly digital blocks for DSP and control. However, specifications of the converters in various applications emphasize high dynamic range and low spurious spectral performance. It is nontrivial to achieve this level of linearity in a monolithic environment where post-fabrication component trimming or calibration is cumbersome to implement for certain applications or/and for cost and manufacturability reasons. Additionally, as CMOS integrated circuits are accomplishing unprecedented integration levels, potential problems associated with device scaling – the short-channel effects – are also looming large as technology strides into the deep-submicron regime. The A/D conversion process involves sampling the applied analog input signal and quantizing it to its digital representation by comparing it to reference voltages before further signal processing in subsequent digital systems. Depending on how these functions are combined, different A/D converter architectures can be implemented with different requirements on each function. Practical realizations show the trend that to a first order, converter power is directly proportional to sampling rate. However, power dissipation required becomes nonlinear as the speed capabilities of a process technology are pushed to the limit. Pipeline and two-step/multi-step converters tend to be the most efficient at achieving a given resolution and sampling rate specification. This thesis is in a sense unique work as it covers the whole spectrum of design, test, debugging and calibration of multi-step A/D converters; it incorporates development of circuit techniques and algorithms to enhance the resolution and attainable sample rate of an A/D converter and to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover and compensate for the errors continuously. The power proficiency for high resolution of multi-step converter by combining parallelism and calibration and exploiting low-voltage circuit techniques is demonstrated with a 1.8 V, 12-bit, 80 MS/s, 100 mW analog to-digital converter fabricated in five-metal layers 0.18-µm CMOS process. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. Microscopic particles present in the manufacturing environment and slight variations in the parameters of manufacturing steps can all lead to the geometrical and electrical properties of an IC to deviate from those generated at the end of the design process. Those defects can cause various types of malfunctioning, depending on the IC topology and the nature of the defect. To relive the burden placed on IC design and manufacturing originated with ever-increasing costs associated with testing and debugging of complex mixed-signal electronic systems, several circuit techniques and algorithms are developed and incorporated in proposed ATPG, DfT and BIST methodologies. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. With the use of dedicated sensors, which exploit knowledge of the circuit structure and the specific defect mechanisms, the method described in this thesis facilitates early and fast identification of excessive process parameter variation effects. The expectation-maximization algorithm makes the estimation problem more tractable and also yields good estimates of the parameters for small sample sizes. To allow the test guidance with the information obtained through monitoring process variations implemented adjusted support vector machine classifier simultaneously minimize the empirical classification error and maximize the geometric margin. On a positive note, the use of digital enhancing calibration techniques reduces the need for expensive technologies with special fabrication steps. Indeed, the extra cost of digital processing is normally affordable as the use of submicron mixed signal technologies allows for efficient usage of silicon area even for relatively complex algorithms. Employed adaptive filtering algorithm for error estimation offers the small number of operations per iteration and does not require correlation function calculation nor matrix inversions. The presented foreground calibration algorithm does not need any dedicated test signal and does not require a part of the conversion time. It works continuously and with every signal applied to the A/D converter. The feasibility of the method for on-line and off-line debugging and calibration has been verified by experimental measurements from the silicon prototype fabricated in standard single poly, six metal 0.09-µm CMOS process