89 research outputs found
RowHammer: Reliability Analysis and Security Implications
As process technology scales down to smaller dimensions, DRAM chips become
more vulnerable to disturbance, a phenomenon in which different DRAM cells
interfere with each other's operation. For the first time in academic
literature, our ISCA paper exposes the existence of disturbance errors in
commodity DRAM chips that are sold and used today. We show that repeatedly
reading from the same address could corrupt data in nearby addresses. More
specifically: When a DRAM row is opened (i.e., activated) and closed (i.e.,
precharged) repeatedly (i.e., hammered), it can induce disturbance errors in
adjacent DRAM rows. This failure mode is popularly called RowHammer. We tested
129 DRAM modules manufactured within the past six years (2008-2014) and found
110 of them to exhibit RowHammer disturbance errors, the earliest of which
dates back to 2010. In particular, all modules from the past two years
(2012-2013) were vulnerable, which implies that the errors are a recent
phenomenon affecting more advanced generations of process technology.
Importantly, disturbance errors pose an easily-exploitable security threat
since they are a breach of memory protection, wherein accesses to one page
(mapped to one row) modifies the data stored in another page (mapped to an
adjacent row).Comment: This is the summary of the paper titled "Flipping Bits in Memory
Without Accessing Them: An Experimental Study of DRAM Disturbance Errors"
which appeared in ISCA in June 201
DNA Pre-alignment Filter using Processing Near Racetrack Memory
Recent DNA pre-alignment filter designs employ DRAM for storing the reference
genome and its associated meta-data. However, DRAM incurs increasingly high
energy consumption background and refresh energy as devices scale. To overcome
this problem, this paper explores a design with racetrack memory (RTM)--an
emerging non-volatile memory that promises higher storage density, faster
access latency, and lower energy consumption. Multi-bit storage cells in RTM
are inherently sequential and thus require data placement strategies to
mitigate the performance and energy impacts of shifting during data accesses.
We propose a near-memory pre-alignment filter with a novel data mapping and
several shift reduction strategies designed explicitly for RTM. On a set of
four input genomes from the 1000 Genome Project, our approach improves
performance and energy efficiency by 68% and 52%, respectively, compared to the
state of the art proposed DRAM-based architecture
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