Interconnect Fabrics for Multi-Core Quantum Processors: A Context Analysis

Quantum computing has revolutionized the field of computer science with its extraordinary ability to handle classically intractable problems. To realize its potential, however, quantum computers need to scale to millions of qubits, a feat that will require addressing fascinating yet extremely challenging interconnection problems. In this paper, we provide a context analysis of the nascent quantum computing field from the perspective of communications, with the aim of encouraging the on-chip networks community to contribute and pave the way for truly scalable quantum computers in the decades to come.Comment: 6 pages, 4 figures; appearing in Proceedings of the IEEE/ACM NoCArc 202

An architecture and technology for Ambient Intelligence Node

The era of separate networks is over. The existing technology leaders are preparing a big change in recreation of environment around us. There are several faces for this change. Names like Ambient Intelligence, Ambient Network, IP Multimedia Subsystem and others were created all over the Globe. Regardless of which name is used the new network will combine three main functional principles---it will be: contextual aware, ubiquitous access and intelligent interfaces unified network. Within this thesis two major aspects are defined. First, the definition of the Ambient Intelligence Environment concept is presented. Secondly the architecture vectors for the technology are named. A short overview of the existing technology is followed by details for the chosen technology---FPGA. The overall specifications are incorporated in the design and demonstration of a basic Ambient Intelligence Node created in the System on the Chip (SoC) FPGA technology

ATAC: A Manycore Processor with On-Chip Optical Network

Ever since industry has turned to parallelism instead of frequency scaling to improve processor performance, multicore processors have continued to scale to larger and larger numbers of cores. Some believe that multicores will have 1000 cores or more by the middle of the next decade. However, their promise of increased performance will only be reached if their inherent scaling and programming challenges are overcome. Meanwhile, recent advances in nanophotonic device manufacturing are making chip-stack optics a reality; interconnect technology which can provide significantly more bandwidth at lower power than conventional electrical analogs. Perhaps more importantly, optical interconnect also has the potential to enable new, easy-to-use programming models enabled by an inexpensive broadcast mechanism. This paper introduces ATAC, a new manycore architecture that capitalizes on the recent advances in optics to address a number of the challenges that future manycore designs will face. The new constraints and opportunities associated with on-chip optical interconnect are presented and explored in the design of ATAC. Furthermore, this paper introduces ACKwise, a novel directory-based cache coherence protocol that takes advantage of the special properties of ATAC to achieve high performance and scalability on large-scale manycores. Early performance results show that a 1000-core ATAC chip achieves a speedup of as much as 39% when compared with a similarly sized manycore with an electrical mesh network

Verifying a Systematic Application to Accelerator Roadmap using Shallow Water Wave Equations

With the advent of parallel computing, a number of hardware architectures have become available for data parallel applications. Every architecture is unique with respect to characteristics such as floating point operations per second, memory bandwidth and synchronization costs. Data parallel applications possess inherent parallelism that needs to be studied and the hardware that can best exploit this parallelism can be identified and selected for large-scale implementation. The application that I have considered for my thesis is - numerical solution of shallow water wave equations using finite difference method. These equations are a set of partial differential equations that model the propagation of disturbances in water and other incompressible liquids. This application fits in the category of a Synchronous Iterative Algorithm (SIA) and hence, the Synchronous Iterative GPGPU Execution (SIGE) model can be directly applied for performance modeling. In the high performance computing community, Graphical Processing Units (GPUs) and Field Programmable Gate Arrays (FPGAs) have become highly popular architectures. Homogeneous clusters comprising of multiple processors and heterogeneous clusters that have nodes consisting of both CPU and GPU, are the architectures of interest for this thesis. An initial or high level comparison between the two architectures is performed with regards to the chosen application using a technique known as the Initial Application to Accelerator (A2A) mapping which ranks which architecture delivers the best performance with respect to execution time for large scale implementation. The subsequent part of the thesis will focus on a low level abstraction of the application of interest to accurately predict the runtime using the multi-level SIGE performance-modeling suite. Through this abstraction, performance modeling of the computation and communication portion of the application is undertaken. The behavior of the computation and communication portions is captured through several instrumented iterations of the application and regression analysis is performed on the execution times. The predicted run time is the sum of the computation and communication run time predictions and is validated by executing the application at higher data sizes. The thesis concludes with the pros and cons of applying the A2A fitness model and the low level abstraction for run time prediction to the chosen application. A critique of the SIGE model is presented and a Strength, Weakness, Opportunities (SWO) analysis is presented

Mixed-mode multicore reliability

Future processors are expected to observe increasing rates of hardware faults. Using Dual-Modular Redundancy (DMR), two cores of a multicore can be loosely coupled to redundantly execute a single software thread, providing very high coverage from many difference sources of faults. This reliability, however, comes at a high price in terms of per-thread IPC and overall system throughput. We make the observation that a user may want to run both applications requiring high reliability, such as financial software, and more fault tolerant applications requiring high performance, such as media or web software, on the same machine at the same time. Yet a traditional DMR system must fully operate in redundant mode whenever any application requires high reliability. This paper proposes a Mixed-Mode Multicore (MMM), which enables most applications, including the system software, to run with high reliability in DMR mode, while applications that need high performance can avoid the penalty of DMR. Though conceptually simple, two key challenges arise: 1) care must be taken to protect reliable applications from any faults occurring to applications running in high performance mode, and 2) the desire to execute additional independent software threads for a performance application complicates the scheduling of computation to cores. After solving these issues, an MMM is shown to improve overall system performance, compared to a traditional DMR system, by approximately 2X when one reliable and one performance application are concurrently executing

HALLS: An Energy-Efficient Highly Adaptable Last Level STT-RAM Cache for Multicore Systems

Spin-Transfer Torque RAM (STT-RAM) is widely considered a promising alternative to SRAM in the memory hierarchy due to STT-RAM's non-volatility, low leakage power, high density, and fast read speed. The STT-RAM's small feature size is particularly desirable for the last-level cache (LLC), which typically consumes a large area of silicon die. However, long write latency and high write energy still remain challenges of implementing STT-RAMs in the CPU cache. An increasingly popular method for addressing this challenge involves trading off the non-volatility for reduced write speed and write energy by relaxing the STT-RAM's data retention time. However, in order to maximize energy saving potential, the cache configurations, including STT-RAM's retention time, must be dynamically adapted to executing applications' variable memory needs. In this paper, we propose a highly adaptable last level STT-RAM cache (HALLS) that allows the LLC configurations and retention time to be adapted to applications' runtime execution requirements. We also propose low-overhead runtime tuning algorithms to dynamically determine the best (lowest energy) cache configurations and retention times for executing applications. Compared to prior work, HALLS reduced the average energy consumption by 60.57% in a quad-core system, while introducing marginal latency overhead.Comment: To Appear on IEEE Transactions on Computers (TC

Standardisation of magnetic nanoparticles in liquid suspension

Suspensions of magnetic nanoparticles offer diverse opportunities for technology innovation, spanning a large number of industry sectors from imaging and actuation based applications in biomedicine and biotechnology, through large-scale environmental remediation uses such as water purification, to engineering-based applications such as position-controlled lubricants and soaps. Continuous advances in their manufacture have produced an ever-growing range of products, each with their own unique properties. At the same time, the characterisation of magnetic nanoparticles is often complex, and expert knowledge is needed to correctly interpret the measurement data. In many cases, the stringent requirements of the end-user technologies dictate that magnetic nanoparticle products should be clearly defined, well characterised, consistent and safe; or to put it another way—standardised. The aims of this document are to outline the concepts and terminology necessary for discussion of magnetic nanoparticles, to examine the current state-of-the-art in characterisation methods necessary for the most prominent applications of magnetic nanoparticle suspensions, to suggest a possible structure for the future development of standardisation within the field, and to identify areas and topics which deserve to be the focus of future work items. We discuss potential roadmaps for the future standardisation of this developing industry, and the likely challenges to be encountered along the way

Standardisation of magnetic nanoparticles in liquid suspension

Suspensions of magnetic nanoparticles offer diverse opportunities for technology innovation, spanning a large number of industry sectors from imaging and actuation based applications in biomedicine and biotechnology, through large-scale environmental remediation uses such as water purification, to engineering-based applications such as position-controlled lubricants and soaps. Continuous advances in their manufacture have produced an ever-growing range of products, each with their own unique properties. At the same time, the characterisation of magnetic nanoparticles is often complex, and expert knowledge is needed to correctly interpret the measurement data. In many cases, the stringent requirements of the end-user technologies dictate that magnetic nanoparticle products should be clearly defined, well characterised, consistent and safe; or to put it another way—standardised. The aims of this document are to outline the concepts and terminology necessary for discussion of magnetic nanoparticles, to examine the current state-of-the-art in characterisation methods necessary for the most prominent applications of magnetic nanoparticle suspensions, to suggest a possible structure for the future development of standardisation within the field, and to identify areas and topics which deserve to be the focus of future work items. We discuss potential roadmaps for the future standardisation of this developing industry, and the likely challenges to be encountered along the way