A VLSI Implementation of a Parallel, Self-Organizing Learning Model

This paper presents a VLSI implementation of the Priority Adaptive Self-Organizing Concurrent System (PASOCS) learning model that is built using a multichip module (MCM) substrate. Many current hardware implementations of neural network learning models are direct implementations of classical neural network structures---a large number of simple computing nodes connected by a dense number of weighted links. PASOCS is one of a class of ASOCS (Adaptive SelfOrganizing Concurrent System) connectionist models whose overall goal is the same as classical neural networks models, but whose functional mechanisms differ significantly. This model has potential application in areas such as pattern recognition, robotics, logical inference, and dynamic control. 1 Introduction Over the past few years, many companies and researchers have announced hardware implementations of neural networks [1, 2, 3, 4]. The integrated circuits (ICs) cited are representative of much current neural network implementatio..