A Study on the Utility of Using Expected Quality Level as a Design for Testability Metric

This paper develops a Physical Design for Test (PDFT) metric that is directly related to the expected quality level (QL) contribution of a cell to a circuit, and it details experimental results showing the usefulness of this metric in predicting the quality level contribution of a cell to circuits that have yet to be designed. The PDFT metric shows what QL increase can be expected for the circuit by changing the physical design of a component of the circuit. 1 Introduction The purpose of physical design for test (PDFT) is to allow IC manufacturers to increase the quality of a shipped product; more formally, to increase the quality level, the fraction of shipped circuits that are faultfree. Traditional approaches to improving quality level have focused on ease-of-detection [4, 5, 11, 13], but the likelihood of occurrence of potential faults is also important: Physical design for test addresses both of these factors. PDFT entails modifying the physical layout of a circuit in order to s..