A Sparsity-Aware MOR Methodology for Fast and Accurate Timing Analysis of VLSI Interconnects

Signoff timing analysis is essential in order to verify the proper operation of VLSI circuits. As process technologies scale down towards nanometer regimes, the fast and accurate timing analysis of interconnects has become crucial, since interconnect delay represents an increasingly dominant portion of the overall circuit delay. It is a common view that traditional SPICE transient simulation of very large interconnect models is not feasible for full-chip timing analysis, while static Elmore-based methods can be inaccurate by orders of magnitude. Model Order Reduction (MOR) techniques are typically employed to provide a good compromise between accuracy and performance. However, all established MOR techniques result in dense system matrices that render their simulation impractical. To this end, in this paper we propose a sparsity-aware MOR methodology for the timing analysis of complex interconnects. Experimental results demonstrate that the proposed method achieves up to 30x simulation time speedups over SPICE transient simulation of the initial model, maintaining a reasonable typical accuracy of 4%. © 2019 IEEE