Time interleaved optical sampling for ultra-high speed A/D conversion

A scheme is proposed for increasing the sampling rate of analogue-to-digital conversion by more than an order of magnitude by combining state-of-the-art A/D converters with photonic technology. Ultra-high speed sampling is performed optically by a multiwavelength pulse train. Wavelength demultiplexers convert the high repetition rate data stream of samples into parallel data streams that can be handled by available electronic A/D converters

Optical IP switching a solution to dynamic lightpath establishment in disaggregated network architectures

The landscape of the telecommunications environment is constantly evolving; in terms of architecture and increasing data-rate. Ensuring that routing decisions are taken at the lowest possible layer offers the possibility of greatest data throughput. We propose using wavelengths in a DWDM scheme as dedicated channels that bypass the routing lookup in a router. The future trend of telecommunications industry is, however, toward larger numbers of interlinked competing operator networks. This in turn means there is a lack of a unified control plane to allow current networks to dynamically provision optical paths. This paper will report on the concept of optical IP switching. This concept seeks to address optical control plane issues in disaggregated networks while providing a means to dynamically provision optical paths to cater for large data flows

Performance modeling and analysis of IP switching

IP switching is a new routing technology proposed to improve the performance of IP routers. In this paper, we study the performance modeling and analysis of IP switching. Our proposed performance models can be used to evaluate the percentage of flows switched and the ratio of the switched path delay to the forwarded path delay in an IP switch. Based on these models, the impacts of different system parameters on the performance are also investigated. Our objective is to develop a design tool for IP switches.published_or_final_versio

Traffic lifetime-aware routing considering dynamic grooming in WDM networks

Master'sMASTER OF ENGINEERIN

System architecture and hardware implementations for a reconfigurable MPLS router

With extremely wide bandwidth and good channel properties, optical fibers have brought fast and reliable data transmission to today’s data communications. However, to handle heavy traffic flowing through optical physical links, much faster processing speed is required or else congestion can take place at network nodes. Also, to provide people with voice, data and all categories of multimedia services, distinguishing between different data flows is a requirement. To address these router performance, Quality of Service /Class of Service and traffic engineering issues, Multi-Protocol Label Switching (MPLS) was proposed for IP-based Internetworks. In addition, routers flexible in hardware architecture in order to support ever-evolving protocols and services without causing big infrastructure modification or replacement are also desirable. Therefore, reconfigurable hardware implementation of MPLS was proposed in this project to obtain the overall fast processing speed at network nodes. The long-term goal of this project is to develop a reconfigurable MPLS router, which uniquely integrates the best features of operations being conducted in software and in run-time-reconfigurable hardware. The scope of this thesis includes system architecture and service algorithm considerations, Verilog coding and testing for an actual device. The hardware and software co-design technique was used to partition and schedule the protocol code for execution on both a general-purpose processor and stream-based hardware. A novel RPS scheme that is practically easy to build and can realize pipelined packet-by-packet data transfer at each output was proposed to take the place of the traditional crossbar switching. In RPS, packets with variable lengths can be switched intelligently without performing packet segmentation and reassembly. Primary theoretical analysis of queuing issues was discussed and an improved multiple queue service scheduling policy UD-WRR was proposed, which can reduce packet-waiting time without sacrificing the performance. In order to have the tests carried out appropriately, dedicated circuitry for the MPLS functional block to interface a specific MAC chip was implemented as well. The hardware designs for all functions were realized with a single Field Programmable Gate Array (FPGA) device in this project. The main result presented in this thesis was the MPLS function implementation realizing a major part of layer three routing at the reconfigurable hardware level, which advanced a great step towards the goal of building a router that is both fast and flexible

On traffic classification and its applications in the Internet

In this work, the methods and applications of traffic classification in the Internet are examined in detail. First, we define and discuss the conceptual environment of traffic classification. We then discuss the performance issues of traffic classification and define a method of visualization to compare the performance of traffic classification implementations. Previously introduced methods of traffic classification: the static applications, the packet count and the list classifiers are compared with each other. We find these methods to perform quite well when analyzed as performing in an IP router, but to be rather ambiguous as to the effect they cause to the user. We introduce an implementation of dynamic traffic classification to two classes using learning vector quantization (LVQ) for flow analysis data and find it to perform well in a simulated environment using flow analysis made on traffic measurements. In comparison to the previous methods of traffic classification, we see that the LVQ classifier has adequate performance. We also study a method of traffic classification using consecutive flow analysis with varying values of the parameters of the flow and find that we are able to classify traffic to 2 or 3 different classes. Within the classes the applications are similar in measured behavior and thus may provide help in realizing some advanced Internet service architectures. Finally, we also observe the application of the dynamic classifier in an Internet router and in the Internet itself. We argue that the implementation of the dynamic classification method is feasible in the network.reviewe

A simulation study of IP switching

Recently there has been much interest in combining the speed of layer-2 switching with the features of layer-3 routing. This has been prompted by numerous proposals, including: IP Switching [1], Tag Switching [2], ARIS [3], CSR [4], and IP over ATM [5]. In this paper, we study IP Switching and evaluate the performance claims made by Newman et al in [1] and [6]. In particular, using ten network traces, we study how well IP Switching performs with traffic found in campus, corporate, and Internet Service Provider (ISP) environments. Our main finding is that IP Switching will lead to a high proportion of datagrams that are switched; over 75% in all of the environments we studied. We also investigate the effects that different flow classifiers and various timer values have on performance, and note that some choices can result in a large VC space requirement. Finally, we present recommendations for the flow classifier and timer values, as a function of the VC space of the switch and the network environment being served

A simulation study of IP switching

Recently there has been much interest in combining the speed of layer-2 switching with the features of layer-3 routing. This has been prompted by numerous proposals, including: IP Switching [l], Tag Switching [2], ARIS [3], CSR [4], and IP over ATM [5]. In this paper, we study IP Switching and evaluate the performance claims made by Newman et al in [l] and [6]. In particular, using ten network traces, we study how well IP Switching performs with traffic found in campus, corporate, and Internet Service Provider (ISP) environments. Our main finding is that IP Switching will lead to a high proportion of datagrams that are switched; over 75% in all of the environments we studied. We also investigate the ef-fects that different flow classifiers and various timer values have on performance, and note that some choices can result in a large VC space requirement. Finally, we present recommendations for the flow classifier and timer values, as a function of the VC space o