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1 research outputs found
A refinement methodology for clock gating optimization at layout level in digital circuits
Author
Benini L.
Bocca Alberto
+6Â more
Bonanno Alberto
Macii Alberto
Macii Enrico
Nagel J.L.
Piguet C.
Poncino Massimo
Publication venue
American Scientific Publishers
Publication date
01/01/2010
Field of study
No full text
PORTO@iris (Publications Open Repository TOrino - Politecnico di Torino)
PORTO Publications Open Repository TOrino