Radiation hard FPGA configuration techniques using silicon on sapphire

 Once entirely the domain of space-borne applications, the effects of high energy charged particles on electronics systems is now also a concern for terrestrial devices. Reconfigurable components such as FPGAs are particularly vulnerable to radiation single event effects (SEU) as they carry a large amount of memory within a relatively small amount of circuit area. This thesis presents a Silicon on Insulator (SOI) based configuration memory system in a radiation hard reconfiguration system. The SOI technology used in this particular work is Silicon on Sapphire, where Sapphire is used as the body insulator. A non-volatile storage cell, able to be manufactured in a standard single polysilicon SOI CMOS process with no special layers, is combined with a Schmitt amplifier which result a final structure that exhibits two unique characteristics enhancing its resistance to radiation. Firstly, it is impossible for a radiation induced event to permanently flip the configuration state. Secondly, a partial de-programming resulting in a reduction in the magnitude of the storage cell voltage causes a large change in static current that can be very easily detected using a conventional sense amplifier. A simple current detector of the type used in conventional RAM circuits allows the configuration memory to be set up to exhibit self-correcting, or “auto-scrubbing” behavior. While the combination of SOI EEPROM and Schmitt exhibits high intrinsic resistance to radiation induced errors, it is still possible for a sequence of two particle strikes to cause the configuration value to be lost. Estimates are made of the Soft error Rate (SER) performance of the overall configuration memory structure. A trial layout of a configurable Look Up Table (LUT) is presented as an example of how the SOS EEPROM configuration cell would be deployed in a real system

A Radiation Hard LUT Block with Auto-Scrubbing

We present a Silicon-on-Insulator based Look-up Table and configuration memory for application within a radiation hard reconfigurable system. The configuration storage includes a non-volatile EEPROM built using a standard single polysilicon Silicon on Insulator CMOS process linked to a Schmitt sense amplifier and transmission gate LUT structure. A simple current detector of the type used in conventional RAM circuits allows the configuration memory to be set up to exhibit self correcting, or "autoscrubbing" behavior. While the SOI EEPROM and Schmitt exhibit high intrinsic resistance to radiation induced errors, it is still possible for a sequence of two particle strikes to cause the configuration value to be lost. We undertake a preliminary analysis of the Single Event error Rate (SER) performance that results from this behavior