A parametrical Architecture for Reed-Solomon Decoders

Reed-Solomon decoders are digital decoders that use RS detecting and correcting of errors codes. RS codes are widely digused in the transmission and storage of digital information and they are often used in concatenated encoding schemes to obtain great correction capabilities and good robustness to burst errors. In this study, a parametrical approach was chosen for decoder implementation at gate-level, based on the Berlekamp algorithm. This means that the decoder structure depends on two parameters: the bit number used for the symbol representation (m), and the error correction capability (t). The obtained architecture is suitable for a large number of Baferent application (inchding high definition digital TI/) and can be quickly synthesised using Synopsys for any required values of m and t