Reconfigurable Computing for Speech Recognition: Preliminary Findings

Continuous real-time speech recognition is a highly computationally-demanding task, but one which can take good advantage of a parallel processing system. To this end, we describe proposals for, and preliminary findings of, research in implementing in programmable logic the decoder part of a speech recognition system. Recognition via Viterbi decoding of Hidden Markov Models is outlined, along with details of current implementations, which aim to exploit properties of the algorithm that could make it well-suited for devices such as FPGAs. The question of how to deal with limited resources, by reconfiguration or otherwise, is also addressed

A Parallel Implementation of a Hidden Markov Model with Duration Modeling for Speech Recognition

Hidden Markov models (HMMs) are currently the most successful paradigm for speech recognition. Although explicit duration continuous HMMs more accurately model speech than HMMs with implicit duration modeling, the cost of accurate duration modeling is often considered prohibitive. This paper describes a parallel implementation of an HMM with explicit duration modeling for spoken language recognition on the MasPar MP-1. The MP-1 is a fine-grained SIMD architecture with 16384 processing elements (PEs) arranged in a 128x128 mesh. By exploiting the massive parallelism of explicit duration HMMs, development and testing is practical even for large amounts of data. The result of this work is a parallel speech recognizer that can train a phone recognizer in real time. We present several extensions that include context dependent modeling, word recognition, and implicit duration HMMs. 1 Introduction While hidden Markov models (HMMs) have been a popular and effective method of recognizing spoken..