A New and Fast Approach to Very Large Scale Integrated Sequential Circuit Test Generation

We present a new approach to automatic test pattern generation for very large scale integrated sequential circuit testing. This approach is more efficient than past test generation methods, since it exploits knowledge of potential circuit defects. Our method motivates a new combinatorial optimization problem, the Tour Covering Problem. We develop heuristics to solve this optimization problem, then apply these heuristics as new test generation procedures. An empirical study comparing our heuristics to existing methods demonstrates the superiority of our approach, since our approach decreases the number of input vectors required for the test, translating into a reduction in the time and money required for testing sequential circuits. Supported by an Office of Naval Research National Defense Science and Engineering Graduate Fellowship. y Supported in part by the Office of Naval Research under grant N00014-91-J-1241 and by the Competitive Semiconductor Manufacturing project by t..