1,280 research outputs found
Defragmenting the Module Layout of a Partially Reconfigurable Device
Modern generations of field-programmable gate arrays (FPGAs) allow for
partial reconfiguration. In an online context, where the sequence of modules to
be loaded on the FPGA is unknown beforehand, repeated insertion and deletion of
modules leads to progressive fragmentation of the available space, making
defragmentation an important issue. We address this problem by propose an
online and an offline component for the defragmentation of the available space.
We consider defragmenting the module layout on a reconfigurable device. This
corresponds to solving a two-dimensional strip packing problem. Problems of
this type are NP-hard in the strong sense, and previous algorithmic results are
rather limited. Based on a graph-theoretic characterization of feasible
packings, we develop a method that can solve two-dimensional defragmentation
instances of practical size to optimality. Our approach is validated for a set
of benchmark instances.Comment: 10 pages, 11 figures, 1 table, Latex, to appear in "Engineering of
Reconfigurable Systems and Algorithms" as a "Distinguished Paper
Bin Packing and Related Problems: General Arc-flow Formulation with Graph Compression
We present an exact method, based on an arc-flow formulation with side
constraints, for solving bin packing and cutting stock problems --- including
multi-constraint variants --- by simply representing all the patterns in a very
compact graph. Our method includes a graph compression algorithm that usually
reduces the size of the underlying graph substantially without weakening the
model. As opposed to our method, which provides strong models, conventional
models are usually highly symmetric and provide very weak lower bounds.
Our formulation is equivalent to Gilmore and Gomory's, thus providing a very
strong linear relaxation. However, instead of using column-generation in an
iterative process, the method constructs a graph, where paths from the source
to the target node represent every valid packing pattern.
The same method, without any problem-specific parameterization, was used to
solve a large variety of instances from several different cutting and packing
problems. In this paper, we deal with vector packing, graph coloring, bin
packing, cutting stock, cardinality constrained bin packing, cutting stock with
cutting knife limitation, cutting stock with binary patterns, bin packing with
conflicts, and cutting stock with binary patterns and forbidden pairs. We
report computational results obtained with many benchmark test data sets, all
of them showing a large advantage of this formulation with respect to the
traditional ones
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