A methodology for automatic hardware synthesis of multiplier-less digital filters with prescribed output accuracy

This paper proposes a methodology for automatic synthesis of digital filters to meet prescribed output accuracy. Given a given frequency domain specification and output accuracy, a multiplier-less digital filter with canonical signed digits (CSD) will first be designed using advanced filter design techniques. A novel algorithm, based on geometric programming and marginal analysis methods, is proposed to optimize the hardware resources in terms of the internal wordlength of the digital filters to meet the prescribed output accuracy. Because of the use of CSD and multiplier block, the hardware resources can be greatly reduced. Using the system coefficients and wordlength information so obtained, a system for generating the corresponding VHDL codes was also developed. Automatic hardware synthesis is then employed to target the design to different platforms. The effectiveness of the proposed methodology is evaluated by the realization of a digital intermediate frequency receiver in field programmable gate arrays. Design results show that, the proposed methodology greatly reduces the design time of the system, while requiring much less hardware resources than conventional methods. ©2006 IEEE.link_to_subscribed_fulltex