On the suitability and development of layout templates for analog layout reuse and layout-aware synthesis

Accelerating the synthesis of increasingly complex analog integrated circuits is key to bridge the widening gap between what we can integrate and what we can design while meeting ever-tightening time-to-market constraints. It is a well-known fact in the semiconductor industry that such goal can only be attained by means of adequate CAD methodologies, techniques, and accompanying tools. This is particularly important in analog physical synthesis (a.k.a. layout generation), where large sensitivities of the circuit performances to the many subtle details of layout implementation (device matching, loading and coupling effects, reliability, and area features are of utmost importance to analog designers), render complete automation a truly challenging task. To approach the problem, two directions have been traditionally considered, knowledge-based and optimization-based, both with their own pros and cons. Besides, recently reported solutions oriented to speed up the overall design flow by means of reuse-based practices or by cutting off time-consuming, error-prone spins between electrical and layout synthesis (a technique known as layout-aware synthesis), rely on a outstandingly rapid yet efficient layout generation method. This paper analyses the suitability of procedural layout generation based on templates (a knowledge-based approach) by examining the requirements that both layout reuse and layout-aware solutions impose, and how layout templates face them. The ability to capture the know-how of experienced layout designers and the turnaround times for layout instancing are considered main comparative aspects in relation to other layout generation approaches. A discussion on the benefit-cost trade-off of using layout templates is also included. In addition to this analysis, the paper delves deeper into systematic techniques to develop fully reusable layout templates for analog circuits, either for a change of the circuit sizing (i.e., layout retargeting) or a change of the fabrication process (i.e., layout migration). Several examples implemented with the Cadence's Virtuoso tool suite are provided as demonstration of the paper's contributions.Ministerio de Educación y Ciencia TEC2004-0175

Practical Techniques for Improving Performance and Evaluating Security on Circuit Designs

As the modern semiconductor technology approaches to nanometer era, integrated circuits (ICs) are facing more and more challenges in meeting performance demand and security. With the expansion of markets in mobile and consumer electronics, the increasing demands require much faster delivery of reliable and secure IC products. In order to improve the performance and evaluate the security of emerging circuits, we present three practical techniques on approximate computing, split manufacturing and analog layout automation. Approximate computing is a promising approach for low-power IC design. Although a few accuracy-configurable adder (ACA) designs have been developed in the past, these designs tend to incur large area overheads as they rely on either redundant computing or complicated carry prediction. We investigate a simple ACA design that contains no redundancy or error detection/correction circuitry and uses very simple carry prediction. The simulation results show that our design dominates the latest previous work on accuracy-delay-power tradeoff while using 39% less area. One variant of this design provides finer-grained and larger tunability than that of the previous works. Moreover, we propose a delay-adaptive self-configuration technique to further improve the accuracy-delay-power tradeoff. Split manufacturing prevents attacks from an untrusted foundry. The untrusted foundry has front-end-of-line (FEOL) layout and the original circuit netlist and attempts to identify critical components on the layout for Trojan insertion. Although defense methods for this scenario have been developed, the corresponding attack technique is not well explored. Hence, the defense methods are mostly evaluated with the k-security metric without actual attacks. We develop a new attack technique based on structural pattern matching. Experimental comparison with existing attack shows that the new attack technique achieves about the same success rate with much faster speed for cases without the k-security defense, and has a much better success rate at the same runtime for cases with the k-security defense. The results offer an alternative and practical interpretation for k-security in split manufacturing. Analog layout automation is still far behind its digital counterpart. We develop the layout automation framework for analog/mixed-signal ICs. A hierarchical layout synthesis flow which works in bottom-up manner is presented. To ensure the qualified layouts for better circuit performance, we use the constraint-driven placement and routing methodology which employs the expert knowledge via design constraints. The constraint-driven placement uses simulated annealing process to find the optimal solution. The packing represented by sequence pairs and constraint graphs can simultaneously handle different kinds of placement constraints. The constraint-driven routing consists of two stages, integer linear programming (ILP) based global routing and sequential detailed routing. The experiment results demonstrate that our flow can handle complicated hierarchical designs with multiple design constraints. Furthermore, the placement performance can be further improved by using mixed-size block placement which works on large blocks in priority

A framework for fine-grain synthesis optimization of operational amplifiers

This thesis presents a cell-level framework for Operational Amplifiers Synthesis (OASYN) coupling both circuit design and layout. For circuit design, the tool applies a corner-driven optimization, accounting for on-chip performance variations. By exploring the process, voltage, and temperature variations space, the tool extracts design worst case solution. The tool undergoes sensitivity analysis along with Pareto-optimality to achieve required specifications. For layout phase, OASYN generates a DRC proved automated layout based on a sized circuit-level description. Morata et al. (1996) introduced an elegant representation of block placement called sequence pair for general floorplans (SP). Like TCG and BSG, but unlike O-tree, B*tree, and CBL, SP is P-admissible. Unlike SP, TCG supports incremental update during operation and keeps the information of the boundary modules as well as their relative positions in the representation. Block placement algorithms that are based on SP use heuristic optimization algorithms, e.g., simulated annealing where generation of large number of sequence pairs are required. Therefore a fast algorithm is needed to generate sequence pairs after each solution perturbation. The thesis presents a new simple and efficient O(n) runtime algorithm for fast realization of incremental update for cost evaluation. The algorithm integrates sequence pair and transitive closure graph advantages into TCG-S* a superior topology update scheme which facilitates the search for optimum desired floorplan. Experiments show that TCG-S* is better than existing works in terms of area utilization and convergence speed. Routing-aware placement is implemented in OASYN, handling symmetry constraints, e.g., interdigitization, common centroid, along with congestion elimination and the enhancement of placement routability

New Cdc Design Tool For Analog Layout Workflow

The placement and routing on CMOS analog layout design had always been a time consuming and irritating process due to large amount of transistor devices placements, arrangements and a lot of critical nets routing constraint. Manual efforts to complete analog layout design took few weeks to months’ time in previous project cycle according to the complexity of the circuit. In the meantime, designer needs to convert the devices from schematic into layout in canvas of layout editor, and then arrange the devices accordingly one by one or group by group by moving the devices in order to complete device placement. While for routing, even though there are different auto-routers in existing layout editing tool, but these routers are mostly developed for digital design and unable to route analog signals precisely especially when there are constraints for the routing like matching and shielding. This research presents a new automation solution, Cartoon Diagram Compiler (CDC) tool that enabling a significant productivity improvement on analog layout design. The automation tool provides capability to drag-and-drop the transistor devices/instance cells from schematics canvas to floor planning canvas and is able to auto-place non-critical cells and devices in a virtual mode before converting into real layout. After the floorplan/placement fulfill the design requirement, topologies generator can be used for quick preview of routing option and auto-router support for constrained (shield critical net) and un-constrained nets routing. The area and routing quality nearly matched with hand-drawn layout. The CDC tool has been compare and evaluated on Intel in-house analog layout design projects. In research evaluation, the average time to complete manual device placement and layout routing required 640 minutes and 554 minutes respectively. With device placement and layout routing process only required 139 minutes and 112 minutes or significant reduction in period of about 5.14x and 6.31x respectively. In conclusion, CDC tool increases the productivity by allowing fully automatic derivation of placement and routing, incremental design updates and smart placement guaranteeing design rule free from violation

Analog layout design automation: ILP-based analog routers

The shrinking design window and high parasitic sensitivity in the advanced technology have imposed special challenges on the analog and radio frequency (RF) integrated circuit design. In this thesis, we propose a new methodology to address such a deficiency based on integer linear programming (ILP) but without compromising the capability of handling any special constraints for the analog routing problems. Distinct from the conventional methods, our algorithm utilizes adaptive resolutions for various routing regions. For a more congested region, a routing grid with higher resolution is employed, whereas a lower-resolution grid is adopted to a less crowded routing region. Moreover, we strengthen its speciality in handling interconnect width control so as to route the electrical nets based on analog constraints while considering proper interconnect width to address the acute interconnect parasitics, mismatch minimization, and electromigration effects simultaneously. In addition, to tackle the performance degradation due to layout dependent effects (LDEs) and take advantage of optical proximity correction (OPC) for resolution enhancement of subwavelength lithography, in this thesis we have also proposed an innovative LDE-aware analog layout migration scheme, which is equipped with our special routing methodology. The LDE constraints are first identified with aid of a special sensitivity analysis and then satisfied during the layout migration process. Afterwards the electrical nets are routed by an extended OPC-inclusive ILP-based analog router to improve the final layout image fidelity while the routability and analog constraints are respected in the meantime. The experimental results demonstrate the effectiveness and efficiency of our proposed methods in terms of both circuit performance and image quality compared to the previous works

Placement techniques in automatic analog layout generation.

模擬電路版圖設計是一個非常複雜和耗時的過程。通常情況下，設計一個高質量的模擬電路版圖需要電子工程師花費幾週甚至更長的時間。模擬電路的電子特性對於電路的細節設計非常敏感，因此，減小電路中的失配現象成為模擬電路版圖設計中一個非常重要的課題。在本論文中，我們提出了一系列實際的佈局技術，來降低電路的失配並提高繞線的成功率。我們可以非常容易的將這些技術整合至一個完整的模擬佈局和佈線的工具中，此工具可以在幾分鐘內生成一個完整的、高質量的模擬電路版圖。同時，該版圖能夠通過設計規則驗證（DRC）和佈局與電路設計一致性檢測（LVS）。模擬結果顯示，它的電路性能能夠與達到甚至超出手工設計的電路版圖。我們的論文主要作出了以下兩方面貢獻。1. 平衡佈局：對於模擬電路中的電子元器件，如電容、電阻、晶體管等進行一維和二維的平衡佈局。電子工程師可以根據不同的設計需求，通過選擇不同的佈局參數來改變電路的佈局排列方式。同時，在模擬退火算法中，我們著重考慮了器件間的匹配以生成高質量的模擬電路佈局。2. 消除阻塞的電路佈局：在模擬電路設計中，我們期望盡量避免在電子元器件密度較高的區域進行繞線。因此，我們需要在電路佈局設計過程中在電子元器件間留有足夠的佈線空間。為達到這個目標，我們提出了更精確的阻塞估計方法和版圖拓展方法，使其能夠生成一個高質量、高繞線成功率的電路佈局結果。為了驗證生成的電路版圖的質量和匹配特性，我們利用蒙地卡羅方法來模擬電路中的製程偏差和失配特性。實驗結果顯示，我們的工具可以在幾分鐘內自動生成高質量的電路版圖，與人工設計通常需要花費數日至數週相比，設計時間大幅縮短，同時電路的匹配特性得以提升。Analog layout design is a complicated and time-consuming process. It often takes couples of weeks for the layout designers to generate a qualied layout. The elec-trical properties of analog circuit are very sensitive to the layout details, and mis-match reduction becomes a very important issue in analog layout design.In this thesis, we will present some practical placement techniques to reduce mismatch and improve routability. These techniques can be easily integrated into a complete analog placement and routing ow, which can produce in just a few min-utes a complete and high quality layout for analog circuits that passes the design rule check, layout-schematic check and with performance veried by simulations. The contents of this thesis will focus on the following two issues:(1) Symmetry Placement: We consider symmetric placement of transistors, re-sistors and capacitors, which includes 1-D symmetry and 2-D symmetry (or called common centroid). Different symmetric placement congurations, derived accord-ing to the practical needs in analog design, are considered for the matching devices in the simulated annealing engine of the placer in order to generate a placement with high quality.(2) Congestion-driven Placement: In analog design, wires are preferred not be routed over active devices, so we need to leave enough spaces properly for routing between the devices during the placement process. To achieve this, we explore congestion estimation and layout expansion during the placement step in order to produce a good and routable solution.In order to verify the quality of the generated layouts in terms of mismatch, we will run Monte Carlo simulations on them with variations in process and mismatch. Experiments show that our methodology can generate high quality layout automatically in just a few minutes while manual design may take couples of days.Detailed summary in vernacular field only.Detailed summary in vernacular field only.Detailed summary in vernacular field only.Detailed summary in vernacular field only.Detailed summary in vernacular field only.Cui, Guxin.Thesis (M.Phil.)--Chinese University of Hong Kong, 2012.Abstracts also in Chinese.Abstract --- p.iAcknowledgement --- p.ivChapter 1 --- Introduction --- p.1Chapter 1.1 --- Background --- p.1Chapter 1.2 --- Physical Design --- p.2Chapter 1.3 --- Analog Placement --- p.4Chapter 1.3.1 --- Methodologies of Analog Placement --- p.4Chapter 1.3.2 --- Symmetry Constraints of Analog Placement --- p.5Chapter 1.4 --- Process Variation and Layout Mismatch --- p.6Chapter 1.4.1 --- Process Variation --- p.6Chapter 1.4.2 --- Random Mismatch and Systematic Mismatch --- p.7Chapter 1.5 --- Monte Carlo Simulation Procedure --- p.9Chapter 1.6 --- Problem Formulation of Placement --- p.9Chapter 1.7 --- Motivations --- p.10Chapter 1.8 --- Contributions --- p.11Chapter 1.9 --- Thesis Organization --- p.12Chapter 2 --- Literature Review on Analog Placement --- p.13Chapter 2.1 --- Topological Representations Handling Symmetry Constraints --- p.14Chapter 2.1.1 --- Symmetry within the Sequence-Pair (SP) Representation . --- p.14Chapter 2.1.2 --- Block Placement with Symmetry Constraints Based on the O-Tree Non-Slicing Representation --- p.16Chapter 2.1.3 --- Placement with Symmetry Constraints for Analog Layout Design Using TCG-S --- p.17Chapter 2.1.4 --- Modeling Non-Slicing Floorplans with Binary Trees --- p.19Chapter 2.1.5 --- Segment Trees Handle Symmetry Constraints --- p.20Chapter 2.1.6 --- Center-based Corner Block List --- p.22Chapter 2.2 --- Other Works on Analog Placement Constraints --- p.25Chapter 2.2.1 --- Deterministic Analog Placement with Hierarchically Bounded Enumeration and Enhanced Shape Functions --- p.25Chapter 2.2.2 --- Analog Placement Based on Symmetry-Island Formulation --- p.27Chapter 2.2.3 --- Heterogeneous B*-Trees for Analog Placement with Symmetry and Regularity Considerations --- p.28Chapter 2.3 --- Summary --- p.31Chapter 3 --- Common-Centroid Analog Placement --- p.32Chapter 3.1 --- Problem Formulation --- p.33Chapter 3.2 --- Overview of Our Work --- p.35Chapter 3.3 --- Handling Common Centroid Constraints in Different Devices --- p.37Chapter 3.3.1 --- Common Centroid Placement of Resistors --- p.38Chapter 3.3.2 --- Common Centroid Placement of Transistors --- p.44Chapter 3.3.3 --- Common Centroid Placement of Capacitors --- p.47Chapter 3.4 --- Congestion Estimation and Layout Expansion --- p.50Chapter 3.4.1 --- Blockage-Aware Congestion Estimation --- p.51Chapter 3.4.2 --- Layout Expansion --- p.56Chapter 3.5 --- Simulated Annealing --- p.59Chapter 3.5.1 --- Types of Moves --- p.59Chapter 3.5.2 --- Handling Devices in Symmetry Group --- p.59Chapter 3.5.3 --- Cost Function of Simulated Annealing --- p.61Chapter 3.6 --- Summary --- p.62Chapter 4 --- Experimental Results and Monte-Carlo Simulations --- p.64Chapter 4.1 --- Study of Congestion-driven Layout Expansion --- p.64Chapter 4.2 --- Monte Carlo Simulations --- p.70Chapter 4.2.1 --- Devices Modeling --- p.70Chapter 4.2.2 --- Study of Layouts with and without Symmetry Groups --- p.71Chapter 4.2.3 --- Study of Layouts with and without Self-Symmetry Devices --- p.73Chapter 4.2.4 --- Study of Layouts with Different Number of Symmetry Groups --- p.74Chapter 4.2.5 --- Study of Large and Small Size Capacitors Array --- p.76Chapter 4.3 --- Comparison of Automatic and Manual Layouts using Monte Carlo Simulations --- p.79Chapter 5 --- Conclusion --- p.86Bibliography --- p.8

A Reuse-based framework for the design of analog and mixed-signal ICs

Despite the spectacular breakthroughs of the semiconductor industry, the ability to design integrated circuits (ICs) under stringent time-to-market (TTM) requirements is lagging behind integration capacity, so far keeping pace with still valid Moore's Law. The resulting gap is threatening with slowing down such a phenomenal growth. The design community believes that it is only by means of powerful CAD tools and design methodologies -and, possibly, a design paradigm shift-that this design gap can be bridged. In this sense, reuse-based design is seen as a promising solution, and concepts such as IP Block, Virtual Component, and Design Reuse have become commonplace thanks to the significant advances in the digital arena. Unfortunately, the very nature of analog and mixed-signal (AMS) design has hindered a similar level of consensus and development. This paper presents a framework for the reuse-based design of AMS circuits. The framework is founded on three key elements: (1) a CAD-supported hierarchical design flow that facilitates the incorporation of AMS reusable blocks, reduces the overall design time, and expedites the management of increasing AMS design complexity; (2) a complete, clear definition of the AMS reusable block, structured into three separate facets or views: the behavioral, structural, and layout facets, the two first for top-down electrical synthesis and bottom-up verification, the latter used during bottom-up physical synthesis; (3) the design for reusability set of tools, methods, and guidelines that, relying on intensive parameterization as well as on design knowledge capture and encapsulation, allows to produce fully reusable AMS blocks. A case study and a functional silicon prototype demonstrate the validity of the paper's proposals.Ministerio de Educación y Ciencia TEC2004-0175