A Memory Efficient Array Architecture for Real-Time Motion Estimation

A new 2-D array architecture for real-time video picture motion estimation is presented. Due to incorporated concepts of video memory distribution and sharing, the architecture ensures feasible solutions for the HDTV picture format with twice lower memory requirements. It features minimal I/O pin count, 100% processor utilization and is quite suitable for VLSI implementation. 1 Introduction 1.1 Motivation Motion estimation is a basic bandwidth compression method used in video-coding systems. Among several computation methods[3], the Full Search Block Matching Algorithm (FBMA) is most popular. Having successive video frames divided into blocks of (N 2 N ) pixels, the FBMA determines a motion vector, v, for every reference block (X) of the current image by comparing it with all candidate blocks (Y ) within the search area surrounding the position of the reference block in the previous frame. Let x(i; j) be the pixels of the reference block, y(i; j) the pixels of the candidate block a..