A low-IF CMOS simultaneous GPS receiver integrated in a multimode transceiver

Abstract -This paper describes a GPS receiver circuit that operates simultaneously with WCDMA/CDMA2000 transceivers. This receiver uses a low-IF architecture to minimize the external passive components. The RF front-end circuit dynamically adjusts the linearity performance based on the instantaneous transmitting power of the integrated transmitter. The receiver measured performances are >80dB gain, 2.0dB noise figure, >20dB image rejection, maximum out-of-band IIP3 is +6dBm. The synthesize features -132dBc/Hz phase noise at 1MHz offset frequency and a total integrated double sideband phase noise of less than -30dBc in the 100Hz to 1MHz band. The receiver is fabricated in a 0.18µm RFCMOS process, and draws 36.7mA at high linearity mode and 27.4mA at low linearity mode using switch mode power supply. Index Terms -Low-IF architecture, GPS receiver, dynamic switching, low noise amplifier, passive mixer