Design of CMOS integrated frequency synthesizers for ultra-wideband wireless communications systems

Ultra¬wide band (UWB) system is a breakthrough in wireless communication, as it provides data rate one order higher than existing ones. This dissertation focuses on the design of CMOS integrated frequency synthesizer and its building blocks used in UWB system. A mixer¬based frequency synthesizer architecture is proposed to satisfy the agile frequency hopping requirement, which is no more than 9.5 ns, three orders faster than conventional phase¬locked loop (PLL)¬based synthesizers. Harmonic cancela¬tion technique is extended and applied to suppress the undesired harmonic mixing components. Simulation shows that sidebands at 2.4 GHz and 5 GHz are below 36 dBc from carrier. The frequency synthesizer contains a novel quadrature VCO based on the capacitive source degeneration structure. The QVCO tackles the jeopardous ambiguity of the oscillation frequency in conventional QVCOs. Measurement shows that the 5¬GHz CSD¬QVCO in 0.18 µm CMOS technology draws 5.2 mA current from a 1.2 V power supply. Its phase noise is ¬120 dBc at 3 MHz offset. Compared with existing phase shift LC QVCOs, the proposed CSD¬QVCO presents better phase noise and power efficiency. Finally, a novel injection locking frequency divider (ILFD) is presented. Im¬plemented with three stages in 0.18 µm CMOS technology, the ILFD draws 3¬mA current from a 1.8¬V power supply. It achieves multiple large division ratios as 6, 12, and 18 with all locking ranges greater than 1.7 GHz and injection frequency up to 11 GHz. Compared with other published ILFDs, the proposed ILFD achieves the largest division ratio with satisfactory locking range

Design of Power-Efficient Optical Transceivers and Design of High-Linearity Wireless Wideband Receivers

The combination of silicon photonics and advanced heterogeneous integration is promising for next-generation disaggregated data centers that demand large scale, high throughput, and low power. In this dissertation, we discuss the design and theory of power-efficient optical transceivers with System-in-Package (SiP) 2.5D integration. Combining prior arts and proposed circuit techniques, a receiver chip and a transmitter chip including two 10 Gb/s data channels and one 2.5 GHz clocking channel are designed and implemented in 28 nm CMOS technology. An innovative transimpedance amplifier (TIA) and a single-ended to differential (S2D) converter are proposed and analyzed for a low-voltage high-sensitivity receiver; a four-to-one serializer, programmable output drivers, AC coupling units, and custom pads are implemented in a low-power transmitter; an improved quadrature locked loop (QLL) is employed to generate accurate quadrature clocks. In addition, we present an analysis for inverter-based shunt-feedback TIA to explicitly depict the trade-off among sensitivity, data rate, and power consumption. At last, the research on CDR-based​ clocking schemes for optical links is also discussed. We introduce prior arts and propose a power-efficient clocking scheme based on an injection-locked phase rotator. Next, we analyze injection-locked ring oscillators (ILROs) that have been widely used for quadrature clock generators (QCGs) in multi-lane optical or wireline transceivers due to their low power, low area, and technology scalability. The asymmetrical or partial injection locking from 2 phases to 4 phases results in imbalances in amplitude and phase. We propose a modified frequency-domain analysis to provide intuitive insight into the performance design trade-offs. The analysis is validated by comparing analytical predictions with simulations for an ILRO-based QCG in 28 nm CMOS technology. This dissertation also discusses the design of high-linearity wireless wideband receivers. An out-of-band (OB) IM3 cancellation technique is proposed and analyzed. By exploiting a baseband auxiliary path (AP) with a high-pass feature, the in-band (IB) desired signal and out-of-band interferers are split. OB third-order intermodulation products (IM3) are reconstructed in the AP and cancelled in the baseband (BB). A 0.5-2.5 GHz frequency-translational noise-cancelling (FTNC) receiver is implemented in 65nm CMOS to demonstrate the proposed approach. It consumes 36 mW without cancellation at 1 GHz LO frequency and 1.2 V supply, and it achieves 8.8 MHz baseband bandwidth, 40dB gain, 3.3dB NF, 5dBm OB IIP3, and −6.5dBm OB B1dB. After IM3 cancellation, the effective OB-IIP3 increases to 32.5 dBm with an extra 34 mW for narrow-band interferers (two tones). For wideband interferers, 18.8 dB cancellation is demonstrated over 10 MHz with two −15 dBm modulated interferers. The local oscillator (LO) leakage is −92 dBm and −88 dB at 1 GHz and 2 GHz LO respectively. In summary, this technique achieves both high OB linearity and good LO isolation

Advanced CMOS Integrated Circuit Design and Application

The recent development of various application systems and platforms, such as 5G, B5G, 6G, and IoT, is based on the advancement of CMOS integrated circuit (IC) technology that enables them to implement high-performance chipsets. In addition to development in the traditional fields of analog and digital integrated circuits, the development of CMOS IC design and application in high-power and high-frequency operations, which was previously thought to be possible only with compound semiconductor technology, is a core technology that drives rapid industrial development. This book aims to highlight advances in all aspects of CMOS integrated circuit design and applications without discriminating between different operating frequencies, output powers, and the analog/digital domains. Specific topics in the book include: Next-generation CMOS circuit design and application; CMOS RF/microwave/millimeter-wave/terahertz-wave integrated circuits and systems; CMOS integrated circuits specially used for wireless or wired systems and applications such as converters, sensors, interfaces, frequency synthesizers/generators/rectifiers, and so on; Algorithm and signal-processing methods to improve the performance of CMOS circuits and systems

The BLIXER, a Wideband Balun-LNA-I/Q-Mixer Topology

This paper proposes to merge an I/Q current-commutating mixer with a noise-canceling balun-LNA. To realize a high bandwidth, the real part of the impedance of all RF nodes is kept low, and the voltage gain is not created at RF but in baseband where capacitive loading is no problem. Thus a high RF bandwidth is achieved without using inductors for bandwidth extension. By using an I/Q mixer with 25% duty-cycle LO waveform the output IF currents have also 25% duty-cycle, causing 2 times smaller DC-voltage drop after IF filtering. This allows for a 2 times increase in the impedance level of the IF filter, rendering more voltage gain for the same supply headroom. The implemented balun-LNA-I/Q-mixer topology achieves > 18 dB conversion gain, a flat noise figure < 5.5 dB from 500 MHz to 7 GHz, IIP2 = +20 dBm and IIP3 = -3 dBm. The core circuit consumes only 16 mW from a 1.2 V supply voltage and occupies less than 0.01 mm2 in 65 nm CMOS

Cmos Rotary Traveling Wave Oscillators (Rtwos)

Rotary Traveling Wave Oscillator (RTWO) represents a transmission line based technology for multi-gigahertz multiple phase clock generation. RTWO is known for providing low jitter and low phase noise signals but the issue of high power consumption is a major drawback in its application. Direction of wave propagation is random and is determined by the least resistance path in the absence of an external direction control circuit. The objective of this research is to address some of the problems of RTWO design, including high power consumption, uncertainty of propagation direction and optimization of design variables. Included is the modeling of RTWO for sensitivity, phase noise and power analysis. Research objectives were met through design, simulation and implementation. Different designs of RTWO in terms of ring size and number of amplifier stages were implemented and tested. Design tools employed include Agilent ADS, Cadence EDA, SONNET and Altium PCB Designer. Test chip was fabricated using IBM 0.18 μm RF CMOS technology. Performance measures of interest are tuning range, phase noise and power consumption. Agilent ADS and SONNET were used for electromagnetic modeling of transmission lines and electromagnetic field radiation. For each design, electromagnetic simulations were carried out followed by oscillation synthesis based on circuit simulation in Cadence Spectre. RTWO frequencies between 2 GHz and 12 GHz were measured based on the ring size of transmission lines. Simulated microstrip transmission line segments had a quality factor between 5.5 and 18. For the various designs, power consumption ranged from 20 mW to 120 mW. Measured phase noise ranged between -123 dBc/Hz and -87 dBc/Hz at 1 MHz offset. Development also included the design of a wide band buffer and a printed circuit board with high signal integrity for accurate measurement of oscillation frequency and other performance measures. Simulated performance, schematics and measurement results are presented

Multipath Miller Compensation for Switched-Capacitor Systems

A hybrid operational amplifier compensation technique using Miller and multipath compensation is presented for multi-stage amplifier designs. Unconditional stability is achieved by the means of pole-zero cancellation where left-half zeros cancel out the non-dominant poles of the operational amplifier. The compensation technique is stable over process, temperature, and voltage variations. Compared to conventional Miller-compensation, the proposed compensation technique exhibits improved settling response for operational amplifiers with the same gain, bandwidth, power, and area. For the same settling time, the proposed compensation technique will require less area and consume less power than conventional Miller-compensation. Furthermore, the proposed technique exhibits improved output slew rate and lower noise over the conventional Miller-compensation technique. Two-stage operational amplifiers were designed in a 0.18µm CMOS process using the proposed technique and conventional Miller-compensated technique. The design procedure for the two-stage amplifier is applicable for higher-order amplifier designs. The amplifiers were incorporated into a switched-capacitor oscillator where the oscillation harmonics are dependent on the settling behaviour of the op amps. The superior settling response of the proposed compensation technique results in a improved output waveform from the oscillator

A jittered-sampling correction technique for ADCs

In Analogue to Digital Converters (ADCs) jittered sampling raises the noise floor; this leads to a decrease in its Signal to Noise ratio (SNR) and its effective number of bits (ENOB). This research studies a technique that compensate for the effects of sampling with a jittered clock. A thorough understanding of sampling in various data converters is complied

올 디지털 클럭 및 데이터 복원 회로를 적용한 고속 광 수신기 설계

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2016. 8. 정덕균.This thesis presents a 22- to 26.5-Gb/s optical receiver with an all-digital clock and data recovery (ADCDR) fabricated in a 65-nm CMOS process. The receiver consists of an optical front-end and a half-rate bang-bang clock and data recovery circuit. The optical front-end achieves low power consumption by using inverter-based amplifiers and realizes sufficient bandwidth by applying several bandwidth extension techniques. In addition, in order to minimize additional jitter at the front-end, not only magnitude and bandwidth but also phase delay responses are considered. The ADCDR employs an LC quadrature digitally-controlled oscillator (LC-QDCO) to achieve a high phase noise figure-of-merit at tens of gigahertz. The recovered clock jitter is 1.28 psrms and the measured jitter tolerance exceeds the tolerance mask specified in IEEE 802.3ba. The receiver sensitivity is 106 and 184 μApk-pk for a bit error rate of 10−12 at data rates of 25 and 26.5 Gb/s, respectively. The entire receiver chip occupies an active die area of 0.75 mm2 and consumes 254 mW at a data rate of 26.5 Gb/s. The energy efficiencies of the front-end and entire receiver at 26.5 Gb/s are 1.35 and 9.58 pJ/bit, respectively.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 5 CHAPTER 2 DESIGN OF OPTICAL FRONT-END 7 2.1 OVERVIEW 7 2.2 BACKGROUND ON OPTICAL FRONT-END 9 2.2.1 PHOTODIODE 9 2.2.2 TRANSIMPEDANCE AMPLIFIER 11 2.2.3 POST AMPLIFIER 17 2.2.4 SHUNT INDUCTIVE PEAKING 25 2.3 CIRCUIT IMPLEMENTATION 29 2.3.1 OVERALL ARCHITECTURE 29 2.3.2 TRANSIMPEDANCE AMPLIFIER 31 2.3.3 POST AMPLIFIER 34 2.4 NOISE ANALYSIS 43 2.4.1 PHOTODIODE 43 2.4.2 OPTICAL FRONT-END 44 2.4.3 SENSITIVITY 46 CHAPTER 3 DESIGN OF ADCDR FOR OPTICAL RECEIVER 48 3.1 OVERVIEW 48 3.2 BACKGROUND ON PLL-BASED ADCDR 51 3.2.1 PHASE DETECTOR 51 3.2.2 DIGITAL LOOP FILTER 54 3.2.3 DIGITALLY-CONTROLLED OSCILLATOR 56 3.2.4 ANALYSIS OF BANG-BANG ADCDR 67 3.3 CIRCUIT IMPLEMENTATION 70 3.3.1 OVERALL ARCHITECTURE 70 3.3.2 PHASE DETECTION LOGIC 75 3.3.3 DIGITAL LOOP FILTER 77 3.3.4 LC QUADRATURE DCO 78 CHAPTER 4 EXPERIMENTAL RESULTS 82 CHAPTER 5 CONCLUSION 90 BIBLIOGRAPHY 92 초록 101Docto