The effectiveness of different test sets for PLAs

It has been theoretically demonstrated that the single stuck-at fault model for a PLA does not cover as many faults as the single crosspoint model. What has not been demonstrated is the real relative effectiveness of test sets generated using these models. This paper presents the results of a study involving presenting a number of test sets to fabricated PLAs to determine their effectiveness. The test sets included weighted random patterns, of particular interest owing to PLAs being random resistant. Details are given of a method to generate weights, taking into account a PLA's structure

Test Procedure for Erasable Programmable Logic Devices

This study was begun to fulfill part of contract number 01-3374 with Sandia National Laboratories in Sandia, New Mexico. A report of the entire projectentitled "Sandia Sea Lance Telemetry Testing" was submitted to Sandia National Laboratories in January, 1987.Electrical Engineerin

A Heuristic Test-Pattern Generator for Programmable Logic Arrays

This paper describes a heuristic method for generating test patternsfor Programmable Logic Arrays (PLAs). Exploiting the regular structure of PLAs, both random and deterministic test-pattern generation techniques are combined to achieve coverage of crosspoint defects. Patterns to select or deselect product terms are generated through direct inspection of an array; test paths to an observable output are established by successive, rapidly converging assignments of primary input values. Results obtained with a PLII program implementation of the method are described; these results demonstrate that the method developed is both effective and computationally inexpensive. introduction Previous work in test-pattern generation [l-51 has shown that random patterns can be used to easily and efficiently achieve stuck fault test coverage in excess of 90 % for most combinational logic networks. Unfortunately, ran-dom patterns have proved to be ineffective for testing faults in Programmable Logic Arrays (PLAs) [5]. In this paper, a heuristic method will be described that exploits the concepts of random test patterns and extends their application to generating tests for PLAs. This method is called PLAITG, an acronym for programmable logic ar-rayitest generator. Random test patterns do not give high test coverage for PLAs mainly because the AND array in a PLA normally has a relatively large number of used crosspoints in each product term (Fig. I). The probability of detecting a miss-ing crosspoint with a random pattern is no better than 112", where n is the number of used crosspoints in the product term. Since n is frequently greater than 10, the test coverage using random tests is quite low. The prob-lem is solved in the PLMTG procedure by deterministi-cally generating embryonic tests for each used crosspoint in the AND array. These tests are then combined using a procedure that exploits the PLA structure and utilizes random input values wherever possible. The following concepts are employed by PLMTG to achieve further efficiencies in test generation and fault evaluation. I Word h

Cost modelling and concurrent engineering for testable design

This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.As integrated circuits and printed circuit boards increase in complexity, testing becomes a major cost factor of the design and production of the complex devices. Testability has to be considered during the design of complex electronic systems, and automatic test systems have to be used in order to facilitate the test. This fact is now widely accepted in industry. Both design for testability and the usage of automatic test systems aim at reducing the cost of production testing or, sometimes, making it possible at all. Many design for testability methods and test systems are available which can be configured into a production test strategy, in order to achieve high quality of the final product. The designer has to select from the various options for creating a test strategy, by maximising the quality and minimising the total cost for the electronic system. This thesis presents a methodology for test strategy generation which is based on consideration of the economics during the life cycle of the electronic system. This methodology is a concurrent engineering approach which takes into account all effects of a test strategy on the electronic system during its life cycle by evaluating its related cost. This objective methodology is used in an original test strategy planning advisory system, which allows for test strategy planning for VLSI circuits as well as for digital electronic systems. The cost models which are used for evaluating the economics of test strategies are described in detail and the test strategy planning system is presented. A methodology for making decisions which are based on estimated costing data is presented. Results of using the cost models and the test strategy planning system for evaluating the economics of test strategies for selected industrial designs are presented