CORE
🇺🇦Â
 make metadata, not war
Services
Services overview
Explore all CORE services
Access to raw data
API
Dataset
FastSync
Content discovery
Recommender
Discovery
OAI identifiers
OAI Resolver
Managing content
Dashboard
Bespoke contracts
Consultancy services
Support us
Support us
Membership
Sponsorship
Community governance
Advisory Board
Board of supporters
Research network
About
About us
Our mission
Team
Blog
FAQs
Contact us
Filters
1 research outputs found
A Floorplan-Driven High-Level Synthesis Algorithm for Multiplexer Reduction Targeting FPGA Designs
Author
Kazushi KAWAMURA
Koichi FUJIWARA
+3Â more
Masao YANAGISAWA
Nozomu TOGAWA
Shin-ya ABE
Publication venue
'Institute of Electronics, Information and Communications Engineers (IEICE)'
Publication date
01/01/2015
Field of study
No full text
Crossref
No full text
