Functionnally asynchronous VLSI cellular array for morphological filtering of images

The design of a fine grain asynchronous VLSI cellular array is presented . It is shown how asynchronism can be exploited at both functional and structural levels . A joint algorithmic-architectural study has led to the fabrication of an integrated circuit including 16x16 processing elements .The data and control paths are designed using a standard-cell approach, combining CMOS and DCVSL (Differential Cascode Voltage Switch Logic) gates . The 800,000 transistor circuit enables real time morphological filtering of images.A travers la présentation de la conception d'un réseau cellulaire VLSI asynchrone à grain fin, il est montré comment la notion d'asynchronisme peut être exploitée à la fois au niveau fonctionnel et au niveau architectural. Une étude conjointe algorithme-architecture a abouti à la conception d'un circuit intégrant 16x16 processeurs élémentaires, Le flot de conception des chemins de données et de contrôle est basé sur une approche « cellules standard » qui combine des portes CMOS et DCVSL (Differential Cascode Voltage Switch Logic). Ce circuit d'environ 800.000 transistors permet de mettre en oeuvre en temps réel des algorithmes itératifs de filtrage morphologique par reconstruction

A fine-grain asynchronous VLSI cellular array processor architecture

The cellular iterative computation model bears upon three broad-ranging application domains: pixel-level image processing, finite-difference approximation of continuum problems (boundary value PDEs) in computational physics, and cellular automata as discrete models of complex locally-interacting systems, aimed at probing their emergent collective properties. The common underlying idea is to compute the global dynamics of a lattice-structured state-space through the iterative propagation of purely local computational dependencies between state-components. A past generation of mesh-connected SIMD array-processors, among which the MPP [Bat 80], CLIP [Pre 84] and CAM [Tof 87] machines, were canonical architectural mappings of this fruitful concept. All were fine-grain synchronous solutions. The new generation of MIMD RISC-based parallel computers that superseded them are essentially coarse-grain and asynchronous; They can simulate a cellular iterative model in a parallel pseudo-synchronous SPMD mode with global coordination mechanisms. A fine-grain asynchronous architectural model departs in a somewhat paradoxical way from these two mainstream approaches. The idea is to match an architecture with a functional concept of a synchronism, specific to cellular relaxation algorithms. As we show in the following, benefits accrue at both levels from this matching