Testable Design of Repeaterless Low Swing On-Chip Interconnect

Repeaterless low swing interconnects use mixed signal circuits to achieve high performance at low power. When these interconnects are used in large scale and high volume digital systems their testability becomes very important. This paper discusses the testability of low swing repeaterless on-chip interconnects with equalization and clock synchronization. A capacitively coupled transmitter with a weak driver is used as the transmitter. The receiver samples the low swing input data at the center of the data eye and converts it to rail to rail levels and also synchronizes the data to the receiver's clock domain. The system is a mixed signal circuit and the digital components are all scan testable. For the analog section, just a DC test has a fault coverage of 50% of the structural faults. Simple techniques allow integration of the analog components into the digital scan chain increasing the coverage to 74%. Finally, a BIST with low overhead enhances the coverage to 95% of the structural faults. The design and simulations have been done in UMC 130 nm CMOS technology.Comment: 6 pages, 9 figure

A Clock Synchronizer for Repeaterless Low Swing On-Chip Links

A clock synchronizing circuit for repeaterless low swing interconnects is presented in this paper. The circuit uses a delay locked loop (DLL) to generate multiple phases of the clock, of which the one closest to the center of the eye is picked by a phase detector loop. The picked phase is then further fine tuned by an analog voltage controlled delay to position the sampling clock at the center of the eye. A clock domain transfer circuit then transfers the sampled data to the receiver clock domain with a maximum latency of three clock cycles. The proposed synchronizer has been designed and fabricated in 130 nm UMC MM CMOS technology. The circuit consumes 1.4 mW from a 1.2 V supply at a data rate of 1.3 Gbps. Further, the proposed synchronizer has been designed and simulated in TSMC 65 nm CMOS technology. Post layout simulations show that the synchronizer consumes 1.5 mW from a 1 V supply, at a data rate of 4 Gbps in this technology.Comment: 11 pages, 25 figure