Obstacle-Avoiding Rectilinear Steiner Minimal Tree Construction

Obstacle-avoiding rectilinear Steiner minimal tree (OARSMT) construction is becoming one of the most sought after problems in modern design flow. In this thesis we present an algorithm to route a multi-terminal net in the presence of obstacles. Ours is a top down approach which includes partitioning the initial solution into subproblems and using obstacle aware version of Fast Lookup Table based Wirelength Estimation (OA-FLUTE) at a lower level to generate an OAST followed by recombining them with some backend refinement. To construct an initial connectivity graph we use a novel obstacle-avoiding spanning graph (OASG) algorithm which is a generalization of Zhou\u27s spanning graph algorithm without obstacle presented in ASPDAC 2001. The runtime complexity of our algorithm is O(n log n)

Routing for analog chip designs at NXP Semiconductors

During the study week 2011 we worked on the question of how to automate certain aspects of the design of analog chips. Here we focused on the task of connecting different blocks with electrical wiring, which is particularly tedious to do by hand. For digital chips there is a wealth of research available for this, as in this situation the amount of blocks makes it hopeless to do the design by hand. Hence, we set our task to finding solutions that are based on the previous research, as well as being tailored to the specific setting given by NXP. This resulted in an heuristic approach, which we presented at the end of the week in the form of a protoype tool. In this report we give a detailed account of the ideas we used, and describe possibilities to extend the approach

Obstacle-avoiding rectilinear Steiner tree.

Li, Liang.Thesis (M.Phil.)--Chinese University of Hong Kong, 2009.Includes bibliographical references (leaves 57-61).Abstract also in Chinese.Abstract --- p.iAcknowledgement --- p.ivChapter 1 --- Introduction --- p.1Chapter 1.1 --- Background --- p.1Chapter 1.1.1 --- Partitioning --- p.1Chapter 1.1.2 --- Floorplanning and Placement --- p.2Chapter 1.1.3 --- Routing --- p.2Chapter 1.1.4 --- Compaction --- p.3Chapter 1.2 --- Motivations --- p.3Chapter 1.3 --- Problem Formulation --- p.4Chapter 1.3.1 --- Properties of OARSMT --- p.4Chapter 1.4 --- Progress on the Problem --- p.4Chapter 1.5 --- Contributions --- p.5Chapter 1.6 --- Thesis Organization --- p.6Chapter 2 --- Literature Review on OARSMT --- p.8Chapter 2.1 --- Introduction --- p.8Chapter 2.2 --- Previous Methods --- p.9Chapter 2.2.1 --- OARSMT --- p.9Chapter 2.2.2 --- Shortest Path Problem with Blockages --- p.13Chapter 2.2.3 --- OARSMT with Delay Minimization --- p.14Chapter 2.2.4 --- OARSMT with Worst Negative Slack Maximization --- p.14Chapter 2.3 --- Comparison --- p.15Chapter 3 --- Heuristic Method --- p.17Chapter 3.1 --- Introduction --- p.17Chapter 3.2 --- Our Approach --- p.18Chapter 3.2.1 --- Handling of Multi-pin Nets --- p.18Chapter 3.2.2 --- Propagation --- p.20Chapter 3.2.3 --- Backtrack --- p.23Chapter 3.2.4 --- Finding MST --- p.26Chapter 3.2.5 --- Local Refinement Scheme --- p.26Chapter 3.3 --- Experimental Results --- p.28Chapter 3.4 --- Summary --- p.28Chapter 4 --- Exact Method --- p.32Chapter 4.1 --- Introduction --- p.32Chapter 4.2 --- Review on GeoSteiner --- p.33Chapter 4.3 --- Overview of our Approach --- p.33Chapter 4.4 --- FST with Virtual Pins --- p.34Chapter 4.4.1 --- Definition of FST --- p.34Chapter 4.4.2 --- Notations --- p.36Chapter 4.4.3 --- Properties of FST with Virtual Pins --- p.36Chapter 4.5 --- Generation of FST with Virtual Pins --- p.46Chapter 4.5.1 --- Generation of FST with Two Pins --- p.46Chapter 4.5.2 --- Generation of FST with 3 or More Pins --- p.48Chapter 4.6 --- Concatenation of FSTs with Virtual Pins --- p.50Chapter 4.7 --- Experimental Results --- p.52Chapter 4.8 --- Summary --- p.53Chapter 5 --- Conclusion --- p.55Bibliography --- p.6

Geometric-based Optimization Algorithms for Cable Routing and Branching in Cluttered Environments

The need for designing lighter and more compact systems often leaves limited space for planning routes for the connectors that enable interactions among the system’s components. Finding optimal routes for these connectors in a densely populated environment left behind at the detail design stage has been a challenging problem for decades. A variety of deterministic as well as heuristic methods has been developed to address different instances of this problem. While the focus of the deterministic methods is primarily on the optimality of the final solution, the heuristics offer acceptable solutions, especially for such problems, in a reasonable amount of time without guaranteeing to find optimal solutions. This study is an attempt to furthering the efforts in deterministic optimization methods to tackle the routing problem in two and three dimensions by focusing on the optimality of final solutions. The objective of this research is twofold. First, a mathematical framework is proposed for the optimization of the layout of wiring connectors in planar cluttered environments. The problem looks at finding the optimal tree network that spans multiple components to be connected with the aim of minimizing the overall length of the connectors while maximizing their common length (for maintainability and traceability of connectors). The optimization problem is formulated as a bi-objective problem and two solution methods are proposed: (1) to solve for the optimal locations of a known number of breakouts (where the connectors branch out) using mixed-binary optimization and visibility notion and (2) to find the minimum length tree that spans multiple components of the system and generates the optimal layout using the previously-developed convex hull based routing. The computational performance of these methods in solving a variety of problems is further evaluated. Second, the problem of finding the shortest route connecting two given nodes in a 3D cluttered environment is considered and addressed through deterministically generating a graphical representation of the collision-free space and searching for the shortest path on the found graph. The method is tested on sample workspaces with scattered convex polyhedra and its computational performance is evaluated. The work demonstrates the NP-hardness aspect of the problem which becomes quickly intractable as added components or increase in facets are considered

Initial detailed routing algorithms

In this work, we present a study of the problem of routing in the context of the VLSI physical synthesis flow. We study the fundamental routing algorithms such as maze routing, A*, and Steiner tree-based algorithms, as well as some global routing algorithms, namely FastRoute 4.0 and BoxRouter 2.0. We dissect some of the major state of the art initial detailed routing tools, such as RegularRoute, TritonRoute, SmartDR and Dr.CU 2.0. We also propose an initial detailed routing flow, and present an implementation of the proposed routing flow, with a track assignment technique that models the problem as an instance of the maximum independent weighted set (MWIS) and utilizes integer linear programming (ILP) as a solver. The implementation of the proposed initial detailed routing flow also includes an implementation of multiple-source and multiple-target A* for terminal andnet connection with adjustable rules and weights. Finally, we also present a study of the results obtained by the implementation of the proposed initial detailed routing flow and a comparison with the ISPD 2019 contest winners, considering the ISPD 2019 and benchmark suite and evaluation tools.Neste trabalho, apresentamos um estudo do problema de roteamento no contexto do fluxo de síntese física de circuitos integrados VLSI. Nós estudamos algoritmos de roteamento fundamentais como roteamento de labirinto, A* e baseados em árvores de Steiner, além de alguns algoritmos de roteamento global como FastRoute 4.0 e BoxRouter 2.0. Nós dissecamos alguns dos principais trabalhos de roteamento detalhado inicial do estado da arte, como RegularRoute, TritonRoute, SmartDR e Dr.CU 2.0. Também propomos um fluxo de roteamento detalhado inicial, e apresentamos uma implementação do fluxo de roteametno proposto, com uma técnica de assinalamento de trilhas que modela o problema como uma instância do problema do conjunto independente de peso máximo e usa programação linear inteira como um resolvedor. A implementação do fluxo de rotemaento detalhado inicial proposto também inclui uma implementação de um A* com múltiplas fontes e múltiplos destinos para conexão de terminais e redes, com regras e pesos ajustáveis. Por fim, nós apresentamos um estudo dos resultados obtidos pela implementação do fluxo de roteamento detalhado inicial proposto e comparamos com os vencedores do ISPD 2019 contest considerando a suíte de teste e ferramentas de avaliação do ISPD 2019

Algorithms for cartographic visualization

Maps are effective tools for communicating information to the general public and help people to make decisions in, for example, navigation, spatial planning and politics. The mapmaker chooses the details to put on a map and the symbols to represent them. Not all details need to be geographic: thematic maps, which depict a single theme or attribute, such as population, income, crime rate, or migration, can very effectively communicate the spatial distribution of the visualized attribute. The vast amount of data currently available makes it infeasible to design all maps manually, and calls for automated cartography. In this thesis we presented efficient algorithms for the automated construction of various types of thematic maps. In Chapter 2 we studied the problem of drawing schematic maps. Schematic maps are a well-known cartographic tool; they visualize a set of nodes and edges (for example, highway or metro networks) in simplified form to communicate connectivity information as effectively as possible. Many schematic maps deviate substantially from the underlying geography since edges and vertices of the original network are moved in the simplification process. This can be a problem if we want to integrate the schematized network with a geographic map. In this scenario the schematized network has to be drawn with few orientations and links, while critical features (cities, lakes, etc.) of the base map are not obscured and retain their correct topological position with respect to the network. We developed an efficient algorithm to compute a collection of non-crossing paths with fixed orientations using as few links as possible. This algorithm approximates the optimal solution to within a factor that depends only on the number of allowed orientations. We can also draw the roads with different thicknesses, allowing us to visualize additional data related to the roads such as trafic volume. In Chapter 3 we studied methods to visualize quantitative data related to geographic regions. We first considered rectangular cartograms. Rectangular cartograms represent regions by rectangles; the positioning and adjacencies of these rectangles are chosen to suggest their geographic locations to the viewer, while their areas are chosen to represent the numeric values being communicated by the cartogram. One drawback of rectangular cartograms is that not every rectangular layout can be used to visualize all possible area assignments. Rectangular layouts that do have this property are called area-universal. We show that area-universal layouts are always one-sided, and we present algorithms to find one-sided layouts given a set of adjacencies. Rectangular cartograms often provide a nice visualization of quantitative data, but cartograms deform the underlying regions according to the data, which can make the map virtually unrecognizable if the data value differs greatly from the original area of a region or if data is not available at all for a particular region. A more direct method to visualize the data is to place circular symbols on the corresponding region, where the areas of the symbols correspond to the data. However, these maps, so-called symbol maps, can appear very cluttered with many overlapping symbols if large data values are associated with small regions. In Chapter 4 we proposed a novel type of quantitative thematic map, called necklace map, which overcomes these limitations. Instead of placing the symbols directly on a region, we place the symbols on a closed curve, the necklace, which surrounds the map. The location of a symbol on the necklace should be chosen in such a way that the relation between symbol and region is as clear as possible. Necklace maps appear clear and uncluttered and allow for comparatively large symbol sizes. We developed algorithms to compute necklace maps and demonstrated our method with experiments using various data sets and maps. In Chapter 5 and 6 we studied the automated creation of ow maps. Flow maps are thematic maps that visualize the movement of objects, such as people or goods, between geographic regions. One or more sources are connected to several targets by lines whose thickness corresponds to the amount of ow between a source and a target. Good ow maps reduce visual clutter by merging (bundling) lines smoothly and by avoiding self-intersections. We developed a new algorithm for drawing ow trees, ow maps with a single source. Unlike existing methods, our method merges lines smoothly and avoids self-intersections. Our method is based on spiral trees, a new type of Steiner trees that we introduced. Spiral trees have an angle restriction which makes them appear smooth and hence suitable for drawing ow maps. We study the properties of spiral trees and give an approximation algorithm to compute them. We also show how to compute ow trees from spiral trees and we demonstrate our approach with extensive experiments

Graphics Processing Unit-Based Computer-Aided Design Algorithms for Electronic Design Automation

The electronic design automation (EDA) tools are a specific set of software that play important roles in modern integrated circuit (IC) design. These software automate the design processes of IC with various stages. Among these stages, two important EDA design tools are the focus of this research: floorplanning and global routing. Specifically, the goal of this study is to parallelize these two tools such that their execution time can be significantly shortened on modern multi-core and graphics processing unit (GPU) architectures. The GPU hardware is a massively parallel architecture, enabling thousands of independent threads to execute concurrently. Although a small set of EDA tools can benefit from using GPU to accelerate their speed, most algorithms in this field are designed with the single-core paradigm in mind. The floorplanning and global routing algorithms are among the latter, and difficult to render any speedup on the GPU due to their inherent sequential nature. This work parallelizes the floorplanning and global routing algorithm through a novel approach and results in significant speedups for both tools implemented on the GPU hardware. Specifically, with a complete overhaul of solution space and design space exploration, a GPU-based floorplanning algorithm is able to render 4-166X speedup, while achieving similar or improved solutions compared with the sequential algorithm. The GPU-based global routing algorithm is shown to achieve significant speedup against existing state-of-the-art routers, while delivering competitive solution quality. Importantly, this parallel model for global routing renders a stable solution that is independent from the level of parallelism. In summary, this research has shown that through a design paradigm overhaul, sequential algorithms can also benefit from the massively parallel architecture. The findings of this study have a positive impact on the efficiency and design quality of modern EDA design flow

High-Performance Placement and Routing for the Nanometer Scale.

Modern semiconductor manufacturing facilitates single-chip electronic systems that only five years ago required ten to twenty chips. Naturally, design complexity has grown within this period. In contrast to this growth, it is becoming common in the industry to limit design team size which places a heavier burden on design automation tools. Our work identifies new objectives, constraints and concerns in the physical design of systems-on-chip, and develops new computational techniques to address them. In addition to faster and more relevant design optimizations, we demonstrate that traditional design flows based on ``separation of concerns'' produce unnecessarily suboptimal layouts. We develop new integrated optimizations that streamline traditional chains of loosely-linked design tools. In particular, we bridge the gap between mixed-size placement and routing by updating the objective of global and detail placement to a more accurate estimate of routed wirelength. To this we add sophisticated whitespace allocation, and the combination provides increased routability, faster routing, shorter routed wirelength, and the best via counts of published techniques. To further improve post-routing design metrics, we present new global routing techniques based on Discrete Lagrange Multipliers (DLM) which produce the best routed wirelength results on recent benchmarks. Our work culminates in the integration of our routing techniques within an incremental placement flow to improve detailed routing solutions, shrink die sizes and reduce total chip cost. Not only do our techniques improve the quality and cost of designs, but also simplify design automation software implementation in many cases. Ultimately, we reduce the time needed for design closure through improved tool fidelity and the use of our incremental techniques for placement and routing.Ph.D.Computer Science & EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/64639/1/royj_1.pd

Algorithm engineering in geometric network planning and data mining

The geometric nature of computational problems provides a rich source of solution strategies as well as complicating obstacles. This thesis considers three problems in the context of geometric network planning, data mining and spherical geometry. Geometric Network Planning: In the d-dimensional Generalized Minimum Manhattan Network problem (d-GMMN) one is interested in finding a minimum cost rectilinear network N connecting a given set of n pairs of points in ℝ^d such that each pair is connected in N via a shortest Manhattan path. The decision version of this optimization problem is known to be NP-hard. The best known upper bound is an O(log^{d+1} n) approximation for d>2 and an O(log n) approximation for 2-GMMN. In this work we provide some more insight in, whether the problem admits constant factor approximations in polynomial time. We develop two new algorithms, a `scale-diversity aware' algorithm with an O(D) approximation guarantee for 2-GMMN. Here D is a measure for the different `scales' that appear in the input, D ∈ O(log n) but potentially much smaller, depending on the problem instance. The other algorithm is based on a primal-dual scheme solving a more general, combinatorial problem - which we call Path Cover. On 2-GMMN it performs well in practice with good a posteriori, instance-based approximation guarantees. Furthermore, it can be extended to deal with obstacle avoiding requirements. We show that the Path Cover problem is at least as hard to approximate as the Hitting Set problem. Moreover, we show that solutions of the primal-dual algorithm are 4ω^2 approximations, where ω ≤ n denotes the maximum overlap of a problem instance. This implies that a potential proof of O(1)-inapproximability for 2-GMMN requires gadgets of many different scales and non-constant overlap in the construction. Geometric Map Matching for Heterogeneous Data: For a given sequence of location measurements, the goal of the geometric map matching is to compute a sequence of movements along edges of a spatially embedded graph which provides a `good explanation' for the measurements. The problem gets challenging as real world data, like traces or graphs from the OpenStreetMap project, does not exhibit homogeneous data quality. Graph details and errors vary in areas and each trace has changing noise and precision. Hence, formalizing what a `good explanation' is becomes quite difficult. We propose a novel map matching approach, which locally adapts to the data quality by constructing what we call dominance decompositions. While our approach is computationally more expensive than previous approaches, our experiments show that it allows for high quality map matching, even in presence of highly variable data quality without parameter tuning. Rational Points on the Unit Spheres: Each non-zero point in ℝ^d identifies a closest point x on the unit sphere S^{d-1}. We are interested in computing an ε-approximation y ∈ ℚ^d for x, that is exactly on S^{d-1} and has low bit-size. We revise lower bounds on rational approximations and provide explicit spherical instances. We prove that floating-point numbers can only provide trivial solutions to the sphere equation in ℝ^2 and ℝ^3. However, we show how to construct a rational point with denominators of at most 10(d-1)/ε^2 for any given ε ∈ (0, 1/8], improving on a previous result. The method further benefits from algorithms for simultaneous Diophantine approximation. Our open-source implementation and experiments demonstrate the practicality of our approach in the context of massive data sets, geo-referenced by latitude and longitude values.Die geometrische Gestalt von Berechnungsproblemen liefert vielfältige Lösungsstrategieen aber auch Hindernisse. Diese Arbeit betrachtet drei Probleme im Gebiet der geometrischen Netzwerk Planung, des geometrischen Data Minings und der sphärischen Geometrie. Geometrische Netzwerk Planung: Im d-dimensionalen Generalized Minimum Manhattan Network Problem (d-GMMN) möchte man ein günstigstes geradliniges Netzwerk finden, welches jedes der gegebenen n Punktepaare aus ℝ^d mit einem kürzesten Manhattan Pfad verbindet. Es ist bekannt, dass die Entscheidungsvariante dieses Optimierungsproblems NP-hart ist. Die beste bekannte obere Schranke ist eine O(log^{d+1} n) Approximation für d>2 und eine O(log n) Approximation für 2-GMMN. Durch diese Arbeit geben wir etwas mehr Einblick, ob das Problem eine Approximation mit konstantem Faktor in polynomieller Zeit zulässt. Wir entwickeln zwei neue Algorithmen. Ersterer nutzt die `Skalendiversität' und hat eine O(D) Approximationsgüte für 2-GMMN. Hierbei ist D ein Maß für die in Eingaben auftretende `Skalen'. D ∈ O(log n), aber potentiell deutlichen kleiner für manche Problem Instanzen. Der andere Algorithmus basiert auf einem Primal-Dual Schema zur Lösung eines allgemeineren, kombinatorischen Problems, welches wir Path Cover nennen. Die praktisch erzielten a posteriori Approximationsgüten auf Instanzen von 2-GMMN verhalten sich gut. Dieser Algorithmus kann für Netzwerk Planungsprobleme mit Hindernis-Anforderungen angepasst werden. Wir zeigen, dass das Path Cover Problem mindestens so schwierig zu approximieren ist wie das Hitting Set Problem. Darüber hinaus zeigen wir, dass Lösungen des Primal-Dual Algorithmus 4ω^2 Approximationen sind, wobei ω ≤ n die maximale Überlappung einer Probleminstanz bezeichnet. Daher müssen potentielle Beweise, die konstante Approximationen für 2-GMMN ausschließen möchten, Instanzen mit vielen unterschiedlichen Skalen und nicht konstanter Überlappung konstruieren. Geometrisches Map Matching für heterogene Daten: Für eine gegebene Sequenz von Positionsmessungen ist das Ziel des geometrischen Map Matchings eine Sequenz von Bewegungen entlang Kanten eines räumlich eingebetteten Graphen zu finden, welche eine `gute Erklärung' für die Messungen ist. Das Problem wird anspruchsvoll da reale Messungen, wie beispielsweise Traces oder Graphen des OpenStreetMap Projekts, keine homogene Datenqualität aufweisen. Graphdetails und -fehler variieren in Gebieten und jeder Trace hat wechselndes Rauschen und Messgenauigkeiten. Zu formalisieren, was eine `gute Erklärung' ist, wird dadurch schwer. Wir stellen einen neuen Map Matching Ansatz vor, welcher sich lokal der Datenqualität anpasst indem er sogenannte Dominance Decompositions berechnet. Obwohl unser Ansatz teurer im Rechenaufwand ist, zeigen unsere Experimente, dass qualitativ hochwertige Map Matching Ergebnisse auf hoch variabler Datenqualität erzielbar sind ohne vorher Parameter kalibrieren zu müssen. Rationale Punkte auf Einheitssphären: Jeder, von Null verschiedene, Punkt in ℝ^d identifiziert einen nächsten Punkt x auf der Einheitssphäre S^{d-1}. Wir suchen eine ε-Approximation y ∈ ℚ^d für x zu berechnen, welche exakt auf S^{d-1} ist und niedrige Bit-Größe hat. Wir wiederholen untere Schranken an rationale Approximationen und liefern explizite, sphärische Instanzen. Wir beweisen, dass Floating-Point Zahlen nur triviale Lösungen zur Sphären-Gleichung in ℝ^2 und ℝ^3 liefern können. Jedoch zeigen wir die Konstruktion eines rationalen Punktes mit Nennern die maximal 10(d-1)/ε^2 sind für gegebene ε ∈ (0, 1/8], was ein bekanntes Resultat verbessert. Darüber hinaus profitiert die Methode von Algorithmen für simultane Diophantische Approximationen. Unsere quell-offene Implementierung und die Experimente demonstrieren die Praktikabilität unseres Ansatzes für sehr große, durch geometrische Längen- und Breitengrade referenzierte, Datensätze

High-performance and Low-power Clock Network Synthesis in the Presence of Variation.

Semiconductor technology scaling requires continuous evolution of all aspects of physical design of integrated circuits. Among the major design steps, clock-network synthesis has been greatly affected by technology scaling, rendering existing methodologies inadequate. Clock routing was previously sufficient for smaller ICs, but design difficulty and structural complexity have greatly increased as interconnect delay and clock frequency increased in the 1990s. Since a clock network directly influences IC performance and often consumes a substantial portion of total power, both academia and industry developed synthesis methodologies to achieve low skew, low power and robustness from PVT variations. Nevertheless, clock network synthesis under tight constraints is currently the least automated step in physical design and requires significant manual intervention, undermining turn-around-time. The need for multi-objective optimization over a large parameter space and the increasing impact of process variation make clock network synthesis particularly challenging. Our work identifies new objectives, constraints and concerns in the clock-network synthesis for systems-on-chips and microprocessors. To address them, we generate novel clock-network structures and propose changes in traditional physical-design flows. We develop new modeling techniques and algorithms for clock power optimization subject to tight skew constraints in the presence of process variations. In particular, we offer SPICE-accurate optimizations of clock networks, coordinated to reduce nominal skew below 5 ps, satisfy slew constraints and trade-off skew, insertion delay and power, while tolerating variations. To broaden the scope of clock-network-synthesis optimizations, we propose new techniques and a methodology to reduce dynamic power consumption by 6.8%-11.6% for large IC designs with macro blocks by integrating clock network synthesis within global placement. We also present a novel non-tree topology that is 2.3x more power-efficient than mesh structures. We fuse several clock trees to create large-scale redundancy in a clock network to bridge the gap between tree-like and mesh-like topologies. Integrated optimization techniques for high-quality clock networks described in this dissertation strong empirical results in experiments with recent industry-released benchmarks in the presence of process variation. Our software implementations were recognized with the first-place awards at the ISPD 2009 and ISPD 2010 Clock-Network Synthesis Contests organized by IBM Research and Intel Research.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/89711/1/ejdjsy_1.pd