Low-Power, High-Speed Transceivers for Network-on-Chip Communication

Networks on chips (NoCs) are becoming popular as they provide a solution for the interconnection problems on large integrated circuits (ICs). But even in a NoC, link-power can become unacceptably high and data rates are limited when conventional data transceivers are used. In this paper, we present a low-power, high-speed source-synchronous link transceiver which enables a factor 3.3 reduction in link power together with an 80% increase in data-rate. A low-swing capacitive pre-emphasis transmitter in combination with a double-tail sense-amplifier enable speeds in excess of 9 Gb/s over a 2 mm twisted differential interconnect, while consuming only 130 fJ/transition without the need for an additional supply. Multiple transceivers can be connected back-to-back to create a source-synchronous transceiver-chain with a wave-pipelined clock, operating with 6sigma offset reliability at 5 Gb/s

Ultra-Low-Power Superconductor Logic

We have developed a new superconducting digital technology, Reciprocal Quantum Logic, that uses AC power carried on a transmission line, which also serves as a clock. Using simple experiments we have demonstrated zero static power dissipation, thermally limited dynamic power dissipation, high clock stability, high operating margins and low BER. These features indicate that the technology is scalable to far more complex circuits at a significant level of integration. On the system level, Reciprocal Quantum Logic combines the high speed and low-power signal levels of Single-Flux- Quantum signals with the design methodology of CMOS, including low static power dissipation, low latency combinational logic, and efficient device count.Comment: 7 pages, 5 figure

Electronic scanning pressure measuring system and transducer package

An electronic scanning pressure system that includes a plurality of pressure transducers is examined. A means obtains an electrical signal indicative of a pressure measurement from each of the plurality of pressure transducers. A multiplexing means is connected for selectivity supplying inputs from the plurality of pressure transducers to the signal obtaining means. A data bus connects the plurality of pressure transducers to the multiplexing means. A latch circuit is connected to supply control inputs to the multiplexing means. An address bus is connected to supply an address signal of a selected one of the plurality of pressure transducers to the latch circuit. In operation, each of the pressure transducers is successively scanned by the multiplexing means in response to address signals supplied on the address bus to the latch circuit

Report of the sensor readout electronics panel

The findings of the Sensor Readout Electronics Panel are summarized in regard to technology assessment and recommended development plans. In addition to two specific readout issues, cryogenic readouts and sub-electron noise, the panel considered three advanced technology areas that impact the ability to achieve large format sensor arrays. These are mega-pixel focal plane packaging issues, focal plane to data processing module interfaces, and event driven readout architectures. Development in each of these five areas was judged to have significant impact in enabling the sensor performance desired for the Astrotech 21 mission set. Other readout issues, such as focal plane signal processing or other high volume data acquisition applications important for Eos-type mapping, were determined not to be relevant for astrophysics science goals

A 24-GHz SiGe Phased-Array Receiver—LO Phase-Shifting Approach

A local-oscillator phase-shifting approach is introduced to implement a fully integrated 24-GHz phased-array receiver using an SiGe technology. Sixteen phases of the local oscillator are generated in one oscillator core, resulting in a raw beam-forming accuracy of 4 bits. These phases are distributed to all eight receiving paths of the array by a symmetric network. The appropriate phase for each path is selected using high-frequency analog multiplexers. The raw beam-steering resolution of the array is better than 10 [degrees] for a forward-looking angle, while the array spatial selectivity, without any amplitude correction, is better than 20 dB. The overall gain of the array is 61 dB, while the array improves the input signal-to-noise ratio by 9 dB

A CMOS 8×8 SPAD array for Time-of-Flight measurement and light-spot statistics

The design and simulation of a CMOS 8 × 8 single photon avalanche diode (SPAD) array is presented. The chip has been fabricated in a 0.18μm standard CMOS technology and implements a double functionality: measuring the Time-of-Flight with the help of a pulsed light source; or computing focal-plane statistics in biomedical imaging applications based on a concentrated light-spot. The incorporation of on-chip processing simplifies the interfacing of the array with the host system. The pixel pitch is 32μm, while the diameter of the quasi-circular active area of the SPADs is 12μm. The 113μm 2 active area is surrounded by a T-well guard ring. The resulting breakdown voltage is 10V with a maximum excess voltage of 1.8V. The pixel incorporates a novel active quenching/reset circuit. The array has been designed to operate with a laser pulsed at 20Mhz. The overall time resolution is 115ps. Focal-plane statistics are obtained in digital format. The maximum throughput of the digital output buffers is 200Mbps.Ministerio de Economía y Competitividad IPT-2011-1625- 430000, IPC-20111009Office of Naval Research (USA) N00014111031