Evaluation of Single-Chip, Real-Time Tomographic Data Processing on FPGA - SoC Devices

A novel approach to tomographic data processing has been developed and evaluated using the Jagiellonian PET (J-PET) scanner as an example. We propose a system in which there is no need for powerful, local to the scanner processing facility, capable to reconstruct images on the fly. Instead we introduce a Field Programmable Gate Array (FPGA) System-on-Chip (SoC) platform connected directly to data streams coming from the scanner, which can perform event building, filtering, coincidence search and Region-Of-Response (ROR) reconstruction by the programmable logic and visualization by the integrated processors. The platform significantly reduces data volume converting raw data to a list-mode representation, while generating visualization on the fly.Comment: IEEE Transactions on Medical Imaging, 17 May 201

Programmable Trigger Logic Unit Based on FPGA Technology

A programmable trigger logic module (TRILOMO) was implemented successfully in an FPGA using their internal look-up tables to save Boolean functions. Up to 16 trigger input signals can be combined logically for a fast trigger decision. The new feature is that the trigger decision is VME register based. The changes are made without modifying the FPGA code. Additionally the module has an excellent signal delay adjustment.Comment: 4 pages, 4 figure

Interconnect yield analysis and fault tolerance for field programmable gate arrays

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Characterization of Hardening by Design Techniques on Commercial, Small Feature Sized Field-Programmable Gate Arrays

In this thesis, a methodology is developed to experimentally test and evaluate a programmable logic device unde r gamma irradiation. The purpose of which is to determine the radiation effects and characterize the improvements of various hardening by design techniques. The techniques analyzed in this thesis include Error Correction Coding (ECC) and Triple Modular Redundancy (TMR). The TMR circuit includes three different functional implementations of adders compared to TMR voted circuits of those same adders. The TMR is implemented with the same functional adders and as a Functional TMR (FTMR) with three different function adders that are voted on. The three functional adders are: a behavioral adder that allows the FPGA synthesis software to create the implementation, a ripple carry adder that consists of multiple single bit full adders linked together, and a carry look ahead adder that operates the fastest by using an algorithm that creates generate and propagate signals. These adders are connected to single voter TMR and FTMR circuits to evaluate the improvements that could be obtained. The ECC circuit includes Block RAM (BRAM) and Distributed RAM memory elements that are loaded both with ECC and non-error corrected data. The circuit is designed to check for errors in memory data, stuck bit values in the memory, and the performance improvements that ECC provides the system

FACTPLA: Functional analysis and the complexity of testing programmable logic array

This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.A computer aided method for analyzing the testability of Programmable Logic Arrays (PLAs) is described. The method, which is based on a functional verification approach, estimates the complexity of testing a PLA according to the amount of single undetectable faults in the array structure. An analytic program (FACTPLA) is developed to predict the above complexity without analyzing the topology of the array as such. Thus, the method is technology invariant and depends only on the functionality of the PLA. The program quantitatively evaluates the effects of undetectable faults and produces some testability measures to manifest these effects. A testability profile for different PLA examples is provided and a number of suggestions for further research to establish definitely the usefulness of some functional properties for testing were made

Survey of multi-function display and control technology

The NASA orbiter spacecraft incorporates a complex array of systems, displays and controls. The incorporation of discrete dedicated controls into a multi-function display and control system (MFDCS) offers the potential for savings in weight, power, panel space and crew training time. The technology applicable to the development of a MFDCS for orbiter application is surveyed. Technology thought to be applicable presently or in the next five years is highlighted. Areas discussed include display media, data handling and processing, controls and operator interactions and the human factors considerations which are involved in a MFDCS design. Several examples of applicable MFDCS technology are described

Application of advanced electronics to a future spacecraft computer design

Advancements in hardware and software technology are summarized with specific emphasis on spacecraft computer capabilities. Available state of the art technology is reviewed and candidate architectures are defined