A design methodology for performance maintenance of 3D Network-on-Chip with multiplexed Through-Silicon Vias

3D integration is an emerging technology that overcomes 2D integration process limitations. The use of short Through-Silicon Vias (TSVs) introduces a significant reduction in routing area, power consumption, and delay. Though, there are still several challenges in 3D integration technology need to be addressed. It is shown in literature that reducing TSV count has a considerable effect in improving yield. The TSV multiplexing technique called TSVBOX was introduced in [1] to reduce the TSV count without affecting the direct benefits of TSVs. The TSVBOX introduces some delay to the signals to be multiplexed. In this paper, we analyse the TSVBOX timing requirements and deduce a design methodology for TSVBOX-based 3D Network-on-Chip (NoC) to overcome the TSVBOX speed degradation. Performance comparisons under different traffic patterns are conducted to verify our solution. We show that TSVBOX-based 3D NoC performance is highly dependent on the NoC traffic pattern and in most simulation scenarios we tried, it shows almost the same performance of the conventional 3D NoC