3 research outputs found

    Multiple voltage scheme with frequency variation for power minimization of pipelined circuits at high-level synthesis

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    High-Level Synthesis (HLS) is defined as a translation process from a behavioral description into structural description. The high-level synthesis process consists of three interdependent phases: scheduling, allocation and binDing The order of the three phases varies depending on the design flow. There are three important quality measures used to support design decision, namely size, performance and power consumption. Recently, with the increase in portability, the power consumption has become a very dominant factor in the design of circuits. The aim of low-power high-level synthesis is to schedule operations to minimize switching activity and select low power modules while satisfying timing constraints. This thesis presents a heuristic that helps minimize power consumption by operating the functional units at multiple voltages and varied clock frequencies. The algorithm presented here deals with pipelined operations where multiple instance of the same operation are carried out. The algorithm was implemented using C++, on LINUX platform

    A constraint driven approach to loop pipelining and register binding

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    Code generation methods for DSP applications ar e hampered by the combination of tight timing constraints imposed by the performance r equirements of DSP algorithms, and resource constraints imposed by a hardware ar chitecture. In this paper, we pr esent a method for register binding and instruction scheduling based on the exploitation and analysis of resource- and timing constraints. The analysis identifies sequencing constraints between operations additional to the precedence constraints. Without the explicit modeling of these sequencing constraints, a scheduler is often not capable of finding a solution that satisfies the timing, resource and register constraints. The presented approach results in an ef ficient method of obtaining high quality instruction schedules with low register requirements.
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