A comparative simulation study of four multilevel DRAMs

Multilevel DRAM (MLDRAM) attempts to increase storage density by recording more than one bit per cell. Several different two-bit-per-cell schemes have been described in the literature; however, it is difficult to compare them directly because the original papers use different technologies and operating conditions. This paper presents a detailed simulation study that compares three published MLDRAM schemes, along with a new MLDRAM scheme that combines the speed of a MLDRAM proposed by Furuyama et al. and the noise cancellation techniques of a MLDRAM proposed by Gillingham. Our SPICE simulation models use the same array size and process models for each to allow us to make direct comparisons. 1