Implementation of Low Power and Area Efficient 2-Bit/Step Asynchronous SAR ADC using Successively Activated Comparators

A low power (0.4-09V) 2-Bit/Step successive approximation register (SAR) analog to digital converter (ADC) is conferred. A 2-Bit/Step operation technique is proposed which implementing a dynamic threshold configuring comparator instead of number of digital to analog converters (DACs). Area and power is reduced by successively activated comparators. Here the second comparator is activated reflecting the preceding comparator’s results. Because the second comparator threshold is configured dynamically for every cycle, only two comparators are required instead of three. By successively activating the comparators, the number of DAC settling is halved, so the power and area overhead is very small and the performance will be increased. The proposed ADC was implemented in a 90nm technology achieved a gain of 35.4 db, power of 0.89 ?w and the conversion time of 0.32ns with a supply voltage of 0.4v. The total core area of this ADC is 7.74 ?m2

Low-Noise Energy-Efficient Sensor Interface Circuits

Today, the Internet of Things (IoT) refers to a concept of connecting any devices on network where environmental data around us is collected by sensors and shared across platforms. The IoT devices often have small form factors and limited battery capacity; they call for low-power, low-noise sensor interface circuits to achieve high resolution and long battery life. This dissertation focuses on CMOS sensor interface circuit techniques for a MEMS capacitive pressure sensor, thermopile array, and capacitive microphone. Ambient pressure is measured in the form of capacitance. This work propose two capacitance-to-digital converters (CDC): a dual-slope CDC employs an energy efficient charge subtraction and dual comparator scheme; an incremental zoom-in CDC largely reduces oversampling ratio by using 9b zoom-in SAR, significantly improving conversion energy. An infrared gesture recognition system-on-chip is then proposed. A hand emits infrared radiation, and it forms an image on a thermopile array. The signal is amplified by a low-noise instrumentation chopper amplifier, filtered by a low-power 30Hz LPF to remove out-band noise including the chopper frequency and its harmonics, and digitized by an ADC. Finally, a motion history image based DSP analyzes the waveform to detect specific hand gestures. Lastly, a microphone preamplifier represents one key challenge in enabling voice interfaces, which are expected to play a dominant role in future IoT devices. A newly proposed switched-bias preamplifier uses switched-MOSFET to reduce 1/f noise inherently.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/137061/1/chaseoh_1.pd

A self-powered single-chip wireless sensor platform

Internet of things” require a large array of low-cost sensor nodes, wireless connectivity, low power operation and system intelligence. On the other hand, wireless biomedical implants demand additional specifications including small form factor, a choice of wireless operating frequencies within the window for minimum tissue loss and bio-compatibility This thesis describes a low power and low-cost internet of things system suitable for implant applications that is implemented in its entirety on a single standard CMOS chip with an area smaller than 0.5 mm2. The chip includes integrated sensors, ultra-low-power transceivers, and additional interface and digital control electronics while it does not require a battery or complex packaging schemes. It is powered through electromagnetic (EM) radiation using its on-chip miniature antenna that also assists with transmit and receive functions. The chip can operate at a short distance (a few centimeters) from an EM source that also serves as its wireless link. Design methodology, system simulation and optimization and early measurement results are presented

Integrated Circuits and Systems for Smart Sensory Applications

Connected intelligent sensing reshapes our society by empowering people with increasing new ways of mutual interactions. As integration technologies keep their scaling roadmap, the horizon of sensory applications is rapidly widening, thanks to myriad light-weight low-power or, in same cases even self-powered, smart devices with high-connectivity capabilities. CMOS integrated circuits technology is the best candidate to supply the required smartness and to pioneer these emerging sensory systems. As a result, new challenges are arising around the design of these integrated circuits and systems for sensory applications in terms of low-power edge computing, power management strategies, low-range wireless communications, integration with sensing devices. In this Special Issue recent advances in application-specific integrated circuits (ASIC) and systems for smart sensory applications in the following five emerging topics: (I) dedicated short-range communications transceivers; (II) digital smart sensors, (III) implantable neural interfaces, (IV) Power Management Strategies in wireless sensor nodes and (V) neuromorphic hardware

Analysis and study of powerefficient sar adc for active rfid sensor

This thesis introduced an energy-efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) specialized to the active sensors for low-power radio frequency identification (RFID) tag system. As part of the Internet of Things (IoT) transformation, RFID is widely used. In the application where the power supply is limited, power consumption is always a notable criterion as analog circuits such as the ADC circuit, regulator circuit, rectifier circuit and radio frequency (RF) are the common power demanding parts in the system. Normally, the requirement for a longer battery performance is closely related to low-power consumption. For the application active RFID sensor in which requires low to moderate resolution and speed as well as low-power consumption, SAR is usually used as its part of the ADC circuit. Therefore, the power-efficient SAR ADC is presented in this work. The block of SAR ADCs such as the comparator block, digital-to-analog converter (DAC) block, and sampler block is designed to meet the requirement of a low-power consumption performance measurement. This thesis at first will explores the differences between multiple ADC techniques in the previous works. The proposed SAR ADC is presented to enhance the power consumption of SAR ADC in the active RFID sensor application through the implementation of a single-input comparator with the switched-capacitor DAC. In this form of architecture, there is only one input to the comparator, and only one set and a split sampling capacitor in the switched capacitor DAC to generate the required reference levels. The difference in input and output voltage of the proposed SAR ADC is the indication for the low-power design. The influence of parasitic capacitance is reduced to the extent of becoming a non-factor. The parameters of the SAR ADC are the resolution of 8-bit, the sampling frequency of 500 kHz, the supply voltage of 1 V, and the 0.18 μm complementary metal-oxide-semiconductor (CMOS) technology. The power consumption of the proposed SAR ADC is 2.3 μW which is estimated at around 25.8% improvement from the previous work. The demands for low-power consumption of RFID active sensor is well examined. The validity of the proposed design has been proven by the simulation results

Low power CMOS IC, biosensor and wireless power transfer techniques for wireless sensor network application

The emerging field of wireless sensor network (WSN) is receiving great attention due to the interest in healthcare. Traditional battery-powered devices suffer from large size, weight and secondary replacement surgery after the battery life-time which is often not desired, especially for an implantable application. Thus an energy harvesting method needs to be investigated. In addition to energy harvesting, the sensor network needs to be low power to extend the wireless power transfer distance and meet the regulation on RF power exposed to human tissue (specific absorption ratio). Also, miniature sensor integration is another challenge since most of the commercial sensors have rigid form or have a bulky size. The objective of this thesis is to provide solutions to the aforementioned challenges

A 16-Channel Neural Recording System-on-Chip With CHT Feature Extraction Processor in 65-nm CMOS

Next-generation invasive neural interfaces require fully implantable wireless systems that can record from a large number of channels simultaneously. However, transferring the recorded data from the implant to an external receiver emerges as a significant challenge due to the high throughput. To address this challenge, this article presents a neural recording system-on-chip that achieves high resource and wireless bandwidth efficiency by employing on-chip feature extraction. Energy-area-efficient 10-bit 20-kS/s front end amplifies and digitizes the neural signals within the local field potential (LFP) and action potential (AP) bands. The raw data from each channel are decomposed into spectral features using a compressed Hadamard transform (CHT) processor. The selection of the features to be computed is tailored through a machine learning algorithm such that the overall data rate is reduced by 80% without compromising classification performance. Moreover, the CHT feature extractor allows waveform reconstruction on the receiver side for monitoring or additional post-processing. The proposed approach was validated through in vivo and off-line experiments. The prototype fabricated in 65-nm CMOS also includes wireless power and data receiver blocks to demonstrate the energy and area efficiency of the complete system. The overall signal chain consumes 2.6 μW and occupies 0.021 mm² per channel, pointing toward its feasibility for 1000-channel single-die neural recording systems

Doctor of Philosophy

dissertationSince the late 1950s, scientists have been working toward realizing implantable devices that would directly monitor or even control the human body's internal activities. Sophisticated microsystems are used to improve our understanding of internal biological processes in animals and humans. The diversity of biomedical research dictates that microsystems must be developed and customized specifically for each new application. For advanced long-term experiments, a custom designed system-on-chip (SoC) is usually necessary to meet desired specifications. Custom SoCs, however, are often prohibitively expensive, preventing many new ideas from being explored. In this work, we have identified a set of sensors that are frequently used in biomedical research and developed a single-chip integrated microsystem that offers the most commonly used sensor interfaces, high computational power, and which requires minimum external components to operate. Included peripherals can also drive chemical reactions by setting the appropriate voltages or currents across electrodes. The SoC is highly modular and well suited for prototyping in and ex vivo experimental devices. The system runs from a primary or secondary battery that can be recharged via two inductively coupled coils. The SoC includes a 16-bit microprocessor with 32 kB of on chip SRAM. The digital core consumes 350 μW at 10 MHz and is capable of running at frequencies up to 200 MHz. The integrated microsystem has been fabricated in a 65 nm CMOS technology and the silicon has been fully tested. Integrated peripherals include two sigma-delta analog-to-digital converters, two 10-bit digital-to-analog converters, and a sleep mode timer. The system also includes a wireless ultra-wideband (UWB) transmitter. The fullydigital transmitter implementation occupies 68 x 68 μm2 of silicon area, consumes 0.72 μW static power, and achieves an energy efficiency of 19 pJ/pulse at 200 MHz pulse repetition frequency. An investigation of the suitability of the UWB technology for neural recording systems is also presented. Experimental data capturing the UWB signal transmission through an animal head are presented and a statistical model for large-scale signal fading is developed

LOW- VOLTAGE HIGH EFFICIENCY ANALOG-TO-DIGITAL CONVERTER FOR BIOMEDICAL SENSOR INTERFACE

Ph.DDOCTOR OF PHILOSOPH