3 research outputs found

    Frequency Synthesizers and Oscillator Architectures Based on Multi-Order Harmonic Generation

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    Frequency synthesizers are essential components for modern wireless and wireline communication systems as they provide the local oscillator signal required to transmit and receive data at very high rates. They are also vital for computing devices and microcontrollers as they generate the clocks required to run all the digital circuitry responsible for the high speed computations. Data rates and clocking speeds are continuously increasing to accommodate for the ever growing demand on data and computational power. This places stringent requirements on the performance metrics of frequency synthesizers. They are required to run at higher speeds, cover a wide range of frequencies, provide a low jitter/phase noise output and consume minimum power and area. In this work, we present new techniques and architectures for implementing high speed frequency synthesizers which fulfill the aforementioned requirements. We propose a new architecture and design approach for the realization of wideband millimeter-wave frequency synthesizers. This architecture uses two-step multi-order harmonic generation of a low frequency phase-locked signal to generate wideband mm-wave frequencies. A prototype of the proposed system is designed and fabricated in 90nm Complementary Metal Oxide Semiconductor (CMOS) technology. Measurement results demonstrated that a very wide tuning range of 5 to 32 GHz can be achieved, which is costly to implement using conventional techniques. Moreover the power consumption per octave resembles that of state-of-the art reports. Next, we propose the N-Push cyclic coupled ring oscillator (CCRO) architecture to implement two high performance oscillators: (1) a wideband N-Push/M-Push CCRO operating from 3.16-12.8GHz implemented by two harmonic generation operations using the availability of different phases from the CCRO, and (2) a 13-25GHz millimeter-wave N-Push CCRO with a low phase noise performance of -118dBc/Hz at 10MHz. The proposed oscillators achieve low phase noise with higher FOM than state of the art work. Finally, we present some improvement techniques applied to the performance of phase locked loops (PLLs). We present an adaptive low pass filtering technique which can reduce the reference spur of integer-N charge-pump based PLLs by around 20dB while maintaining the settling time of the original PLL. Another PLL is presented, which features very low power consumption targeting the Medical Implantable Communication Standard. It operates at 402-405 MHz while consuming 600microW from a 1V supply

    Analysis and Design of Radio Frequency Integrated Circuits for Breast Cancer Radar Imaging in CMOS Technology

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    Breast cancer is by far the most incident tumor among female population. Early stage prevention is a key factor in delivering long term survival of breast cancer patients. X-ray mammography is the most commonly used diagnostic technique to detect non-palpable tumors. However, 10-30% of tumors are missed by mammography and ionizing radiations together with breast compression do not lead to comfort in patient treatment. In this context, ultrawideband microwave radar technology is an attractive alternative. It relies on the dielectric contrast of normal and malignant tissues at microwave frequencies to detect and locate tumors inside the breast. This work presents the analysis and design of radio frequency integrated circuits for breast cancer imaging in CMOS technology. The first part of the thesis concerns the system analysis. A behavioral model of two different transceiver architectures for UWB breast cancer imaging employing a SFCW radar system are presented. A mathematical model of the direct conversion and super heterodyne architectures together with a numerical breast phantom are developed. FDTD simulations data are used to on the behavioral model to investigate the limits of both architectures from a circuit-level point of view. Insight is given into I/Q phase inaccuracies and their impact on the quality of the final reconstructed images. The result is that the simplicity of the direct conversion architecture makes the receiver more robust toward the critical impairments for this application. The second part of the thesis is dedicated to the circuit design. The main achievement is a 65nm CMOS 2-16GHz stepped frequency radar transceiver for medical imaging. The RX features 36dB conversion gain, >29dBm compression point, 7dB noise figure, and 30Hz 1/f noise corner. The TX outputs 14dBm with >40dBc harmonic rejection and <109dBc/Hz phase noise at 1MHz offset. Overall power dissipation is 204mW from 1.2V supply. The radar achieves 3mm resolution within the body, and 107dB dynamic range, a performance enabling the use for breast cancer diagnostic imaging. To further assess the capabilities of the proposed radar, a physical breast phantom was synthesized and two targets mimicking two tumors were buried inside the breast. The targets are clearly identified and correctly located, effectively proving the performance of the designed radar as a possible tool for breast cancer detection
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