A 70 pJ/b configurable 64-QAM soft MIMO detector

An area and power efficient high-throughput VLSI implementation of a 4 × 4, 64-QAM soft multiple-input-multiple-output (MIMO) detector, that is suitable for high-order constellation schemes is presented. The proposed MIMO detector utilizes information contained in the discarded paths to improve the bit-error-rate (BER) performance, and then reduces computational complexity using three innovative improvement ideas. The proposed design is fabricated and fully tested in a 130 nm CMOS technology. Operating with a 270 MHz clock, the design achieves up to 655 Mbps throughput with 195 mW power dissipation at 1.32 V supply. Synthesis results in 65 nm CMOS technology shows that the proposed soft-output MIMO detector attains a peak coded data throughput of 2 Gbps. Furthermore, this detector is also suitable for low-power mobile applications that require high data rates, achieving a low decoding energy per bit of 70.3 pJ/bit at 1.1 V supply, while providing a data throughput of 640 Mbps in a 65 nm CMOS technology. The proposed design has the best throughput per unit area among all reported fabricated designs to-dat

Design Exploration & Enhancements for Low Complexity Massive MIMO Detectors with High Modulation Order

Global energy consumed by communication and information technologies is expected to increase rapidly due to continuous usage of wireless standards and the expansion for their requirements [1]. In the next generation wireless communications, Multi Input and Multi Output (MIMO) systems are most promising technology to achieve high spectral efficiencies, while going past various challenges like resource and energy constraints [2]. There exists many detection algorithms like Maximum Likelihood (ML), Zero Forcing (ZF), Minimum Mean Square Error (MMSE) which have low silicon complexity but consume significant power for high-end MIMO systems, due to their high computational complexity. And then there are certain low power detection algorithms like real domain breadth first search K-best, with either conventional enumeration or Schnorr Euchner (SE) based enumeration. This improvement through either, comes with cost of comparatively high silicon complexity and sacrifices the performance in terms of detection bit error rate (BER). The complex domain equivalent may improve the BER performance but it’s dedicated algorithm ensures even higher silicon complexity. Several modifications have been performed on original complex domain K-best algorithm to decrease its high silicon complexity, retaining the better performance of the system. This work focuses on study and implementation of original real SE based K-best algorithm [3]. It also features my attempt to perform theoretical analysis of original complex domain detection algorithm, and to implement modified [4] and improved versions of complex domain to decrease its high silicon complexity, retaining BER performance. This work also focuses on exploration and implementation of past attempts on design modifications of complex domain algorithms and compare them across different attributes such as performance, computational and silicon complexity. Few system level and algorithmic level enhancements have been proposed and implemented for low complexity detectors explored. Dynamic fixed point iterative version of original real domain detector [3] has been studied and implemented, along with possible enhancements for complex domain detector. Pipelined hardware architecture of real domain SE based K-best detector [5] has also been studied as part of this work, with the intention of extending this to dynamic fixed point version and also complex domain detector

Baseband Processing for 5G and Beyond: Algorithms, VLSI Architectures, and Co-design

In recent years the number of connected devices and the demand for high data-rates have been significantly increased. This enormous growth is more pronounced by the introduction of the Internet of things (IoT) in which several devices are interconnected to exchange data for various applications like smart homes and smart cities. Moreover, new applications such as eHealth, autonomous vehicles, and connected ambulances set new demands on the reliability, latency, and data-rate of wireless communication systems, pushing forward technology developments. Massive multiple-input multiple-output (MIMO) is a technology, which is employed in the 5G standard, offering the benefits to fulfill these requirements. In massive MIMO systems, base station (BS) is equipped with a very large number of antennas, serving several users equipments (UEs) simultaneously in the same time and frequency resource. The high spatial multiplexing in massive MIMO systems, improves the data rate, energy and spectral efficiencies as well as the link reliability of wireless communication systems. The link reliability can be further improved by employing channel coding technique. Spatially coupled serially concatenated codes (SC-SCCs) are promising channel coding schemes, which can meet the high-reliability demands of wireless communication systems beyond 5G (B5G). Given the close-to-capacity error correction performance and the potential to implement a high-throughput decoder, this class of code can be a good candidate for wireless systems B5G. In order to achieve the above-mentioned advantages, sophisticated algorithms are required, which impose challenges on the baseband signal processing. In case of massive MIMO systems, the processing is much more computationally intensive and the size of required memory to store channel data is increased significantly compared to conventional MIMO systems, which are due to the large size of the channel state information (CSI) matrix. In addition to the high computational complexity, meeting latency requirements is also crucial. Similarly, the decoding-performance gain of SC-SCCs also do come at the expense of increased implementation complexity. Moreover, selecting the proper choice of design parameters, decoding algorithm, and architecture will be challenging, since spatial coupling provides new degrees of freedom in code design, and therefore the design space becomes huge. The focus of this thesis is to perform co-optimization in different design levels to address the aforementioned challenges/requirements. To this end, we employ system-level characteristics to develop efficient algorithms and architectures for the following functional blocks of digital baseband processing. First, we present a fast Fourier transform (FFT), an inverse FFT (IFFT), and corresponding reordering scheme, which can significantly reduce the latency of orthogonal frequency-division multiplexing (OFDM) demodulation and modulation as well as the size of reordering memory. The corresponding VLSI architectures along with the application specific integrated circuit (ASIC) implementation results in a 28 nm CMOS technology are introduced. In case of a 2048-point FFT/IFFT, the proposed design leads to 42% reduction in the latency and size of reordering memory. Second, we propose a low-complexity massive MIMO detection scheme. The key idea is to exploit channel sparsity to reduce the size of CSI matrix and eventually perform linear detection followed by a non-linear post-processing in angular domain using the compressed CSI matrix. The VLSI architecture for a massive MIMO with 128 BS antennas and 16 UEs along with the synthesis results in a 28 nm technology are presented. As a result, the proposed scheme reduces the complexity and required memory by 35%–73% compared to traditional detectors while it has better detection performance. Finally, we perform a comprehensive design space exploration for the SC-SCCs to investigate the effect of different design parameters on decoding performance, latency, complexity, and hardware cost. Then, we develop different decoding algorithms for the SC-SCCs and discuss the associated decoding performance and complexity. Also, several high-level VLSI architectures along with the corresponding synthesis results in a 12 nm process are presented, and various design tradeoffs are provided for these decoding schemes