An Ultra-Miniaturised CMOS Clock and Data Recovery System for Wireless ASK Transmission

Over the years, several clock and data recovery architectures have been proposed for wireless Amplitude Shift Keying (ASK) transmitted signals. State-of-the-art architectures mainly rely on synchronous phase-locked loop circuits or self- sampling systems, both resulting in large area consumption. This work presents a novel CMOS architecture for Clock and Data Recovery (CDR) in miniaturised and wirelessly powered implants. The proposed CDR architecture works at 433.92 MHz and includes: an ASK-demodulator, an on-chip oscillator, a power-on-reset, a control and a recovering block operating in feedback-loop. The ASK-demodulator works for a data rate as high as 6 Mbps and a modulation index in the range of 9-30%. A novel communication protocol is presented for a separated clock and data transmission. The entire CDR architecture occupies 17×89μm2 and consumes 15.01μW while operating with a clock rate of 6 Mbps

Signal-Processing-Driven Integrated Circuits for Energy Constrained Microsystems.

The exponential growth in IC technology has enabled low-cost and increasingly capable wireless sensor nodes which provide a promising way forward to realize the vision of a trillion connected sensors in the next decade. However there are still many design challenges ahead to make these sensor nodes small,low-cost,secure,reliable and energy-efficient to name a few. Since the wireless nodes are expected to operate on a limited energy source or in some cases on harvested energy, the energy consumption of each building block is of prime importance to prolong the life of a sensor node. It has been found that the radio communication when active has been one of the highest power consuming modules on a sensor node. Low-energy protocols, e.g. processing the raw sensor data on-node, are more energy efficient for some applications as compared to transmitting the raw data over a wireless channel to a cloud server. In this thesis we explore signal processing techniques to realize a low power radio solution for wireless communication. Two prototype chips have been designed and their performance has been evaluated. The first prototype chip exploits compressed sensing for Ultra-Wide-Band (UWB) communication. UWB signals typically require a high ADC sampling rate in the receiver which results in high power consumption. Compressed sensing is demonstrated to relax the ADC sampling rate to save power. The second prototype chip exploits the sensitivity vs. power trade-off in a radio receiver to achieve iso-performance at lower power consumption and the time-varying wireless channel characteristics are used to adapt the sampling frequency of the receiver based on the SNR/Link quality of the communication channel, saving power, while maintaining the desired system performance. It is envisioned that embedded machine learning will play a key role in the integration of sensory data with prior knowledge for distributed intelligent sensing which might enable reduced wireless network traffic to a cloud server. A Near-Threshold hardware accelerator for arbitrary Bayesian network was designed for clique-tree message passing algorithm used for probabilistic inference. The hardware accelerator was benchmarked by the mid-size ALARM Bayesian network with total energy consumption of 76nJ for 250µS execution time.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/107130/1/oukhan_1.pd