Ultra Low Power Analog Circuits for Wireless Sensor Node System.

This thesis will discuss essential analog circuit blocks required in ultra-low power wireless sensor node systems. A wireless sensor network system requires very high energy and power efficiency which is difficult to achieve with traditional analog circuits. First, 5.58nW real time clock using a DLL (Delay Locked Loop)-assisted pulse-driven crystal oscillator is discussed. In this circuit, the operational amplifier used in the traditional circuit was replaced with pulsed drivers. The pulse was generated at precise timing by a DLL. The circuit parts operate in different supply levels, generated on chip by using a switched capacitor network. The circuit was tested at different supply voltage and temperature. Its frequency characteristic along with power consumption were measured and compared to the traditional circuit. Next, a Schmitt trigger based pulse-driven crystal oscillator is discussed. In the first chapter, a DLL was used to generate a pulse with precise timing. However, testing results and recent study showed that the crystal oscillator can sustain oscillation even with inaccurate pulse timing. In this chapter, pulse location is determined by the Schmitt trigger. Simulation results show that this structure can still sustain oscillation at different process corners and temperature. In the next chapter, a sub-nW 8 bit SAR ADC (Successive Approximation Analog-to-Digital Converter) using transistor-stack DAC (Digital-to-Analog Converter) is discussed. To facilitate design effort and reduce the layout dependent effect, a conventional capacitive DAC was replaced with transistor-stack DAC with a 255:1 multiplexer. The control logic was designed with both TSPC (True Single Phase Clock) and CMOS logic to minimize transistor count. The ADC was implemented in a 65nm CMOS process and tested at different sampling rates and input signal frequency. Its linearity and power consumption was measured. Also, a similar design was implemented and tested using 180nm CMOS process as part of a sensor node system. Lastly, a multiple output level voltage regulator using a switched capacitor network for low-cost system is discussed.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/111626/1/dmyoon_1.pd

Sensors and analog-to-information converters

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.Cataloged from PDF version of thesis.Includes bibliographical references (p. 93-96).Compressed sensing (CS) is a promising method for recovering sparse signals from fewer measurements than ordinarily used in the Shannon's sampling theorem [14]. Introducing the CS theory has sparked interest in designing new hardware architectures which can be potential substitutions for traditional architectures in communication systems. CS-based wireless sensors and analog-to-information converters (AIC) are two examples of CS-based systems. It has been claimed that such systems can potentially provide higher performance and lower power consumption compared to traditional systems. However, since there is no end-to-end hardware implementation of these systems, it is difficult to make a fair hardware-to-hardware comparison with other implemented systems. This project aims to fill this gap by examining the energy-performance design space for CS in the context of both practical wireless sensors and AICs. One of the limitations of CS-based systems is that they employ iterative algorithms to recover the signal. Since these algorithms are slow, the hardware solution has become crucial for higher performance and speed. In this work, we also implement a suitable CS reconstruction algorithm in hardware.by Omid Salehi-Abari.S.M