A 31.25/125MSps Continuous-Time Delta-Sigma ADC with 64/59dB SNDR in 130nm CMOS

A order 3-bit continuous-time (CT) ΔΣ ADC is presented in this paper. The design equations starting from a discrete-time reference modulator to the circuit implementation are given. The non-return to zero (NRZ) DAC pulses have a half clock cycle loopdelay which is corrected by the feedforward (also known as PI) loop delay compensation, and nonlinearities in the DACs are suppressed by data-weighted averaging. The fabricated 130nm design operates at 31.25/125MHz at a power consumption of 6.04/6.32mA from a 1.2V supply, and achieves an SNDR of 64/59dB at an OSR of 32, resulting in an FOM of 5.73/2.67pJ/cony. step