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Low-Power 12-bit Quasi-Passive Segmented DAC Implemented in 130nm CMOS Technology
This thesis work proposes a low-power 12-bit digital-to-analog converter (DAC) designed in a 130nm process. The DAC to be presented is of a segmented design where the architecture is split into pipelined and thermometer coded segments. This allows for high linearity and low distortion while maintaining high speed and low area. Since the DAC will be utilize a switched capacitor design, an output buffer stage is added to allow for a wide range of loads. Correlated double sampling (CDS) and correlated level shifting (CLS) are implemented to relax operational amplifier specifications and improve buffer performance. Data weighted averaging (DWA) is implemented to mitigate capacitor mismatch errors due process limitations in fabrication. Static and dynamic simulations are performed as well as mismatch sensitivity analyzed