Design and Develop Efficient Arbitration Technique to Handle the Multiple Refresh Requests in Multi-Processor SoC

Emerging memory technologies, such as Gain Cell-embedded Dynamic Random Access Memory (GC-eDRAM), play an essential part in the process of improving the overall performance of current multi-processor systems. GC-eDRAM, on the other hand, has its own set of distinct issues, particularly with regard to refresh operations. The number of cores and threads in contemporary processors continues to expand, which in turn leads to an increase in the number of concurrent refresh requests. This might cause contention, which in turn can lead to a possible performance decrease. In this article, we present an efficient arbitration method that was developed in order to precisely address the issues that are associated with numerous requests for a refresh in GC-eDRAM. This method takes use of the inherent parallelism of GC-eDRAM modules to make it possible to execute simultaneous refresh operations. As a result, contention is effectively reduced, and the overall performance of the system is improved. We provide a new arbitration method that prioritizes the pending refresh requests according to their level of urgency and optimizes the allocation of GC-eDRAM resources in order to guarantee that refresh operations are carried out in an effective manner. Our method modifies the arbitration priority in a dynamic manner according to the characteristics of the active workload. These characteristics include the request arrival rate, memory access patterns, and data location, among other considerations

A 24 kb Single-Well Mixed 3T Gain-Cell eDRAM with Body-Bias in 28 nm FD-SOI for Refresh-Free DSP Applications

Logic-compatible gain-cell embedded DRAM (GC-eDRAM) is an emerging alternative to conventional SRAM for memory-dominated system-on-chip (SoC) designs due to its high-density, low-power, and two-ported operation. Although GCs have a limited data retention time (DRT) at deeply scaled technology nodes, there are many DSP applications which only require short-term data storage and can therefore avoid refresh. In this paper, we present a novel single-well mixed 3T GC implementation in 28 nm FD-SOI technology. The proposed GC is supplied with body-bias control to improve the DRT by suppressing the leakage through the write port, and extend the maximum operating frequency by forward body-biasing the read port. A 24 kbit GC-eDRAM macro implementing the proposed 3T GC was fabricated in 28 nm FD-SOI technology, resulting in the highest density logic-compatible embedded memory fabricated in any 28 nm process with over 2x higher density compared to a 6T SRAM cell, over 4x higher DRT compared to a conventional 3T GC, and 38 x 47 x lower static power compared to conventional single-ported and two-ported SRAMs