A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects

Interconnect architectures which leverage high-bandwidth optical channels offer a promising solution to address the increasing chip-to-chip I/O bandwidth demands. This paper describes a dense, high-speed, and low-power CMOS optical interconnect transceiver architecture. Vertical-cavity surface-emitting laser (VCSEL) data rate is extended for a given average current and corresponding reliability level with a four-tap current summing FIR transmitter. A low-voltage integrating and double-sampling optical receiver front-end provides adequate sensitivity in a power efficient manner by avoiding linear high-gain elements common in conventional transimpedance-amplifier (TIA) receivers. Clock recovery is performed with a dual-loop architecture which employs baud-rate phase detection and feedback interpolation to achieve reduced power consumption, while high-precision phase spacing is ensured at both the transmitter and receiver through adjustable delay clock buffers. A prototype chip fabricated in 1 V 90 nm CMOS achieves 16 Gb/s operation while consuming 129 mW and occupying 0.105 mm^2

Low Power Clock and Data Recovery Integrated Circuits

Advances in technology and the introduction of high speed processors have increased the demand for fast, compact and commercial methods for transferring large amounts of data. The next generation of the communication access network will use optical fiber as a media for data transmission to the subscriber. In optical data or chip-to-chip data communication, the continuous received data needs to be converted to discrete data. For the conversion, a synchronous clock and data are required. A clock and data recovery (CDR) circuit recovers the phase information from the data and generates the in-phase clock and data. In this dissertation, two clock and data recovery circuits for Giga-bits per second (Gbps) serial data communication are designed and fabricated in 180nm and 90nm CMOS technology. The primary objective was to reduce the circuit power dissipation for multi-channel data communication applications. The power saving is achieved using low swing voltage signaling scheme. Furthermore, a novel low input swing Alexander phase detector is introduced. The proposed phase detector reduces the power consumption at the transmitter and receiver blocks. The circuit demonstrates a low power dissipation of 340µW/Gbps in 90nm CMOS technology. The CDR is able to recover the input signal swing of 35mVp. The peak-to-peak jitter is 21ps and RMS jitter is 2.5ps. Total core area excluding pads is approximately 0.01mm2

Design and demonstration of integrated micro-electro-mechanical relay circuits for VLSI applications

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.Cataloged from PDF version of thesis.Includes bibliographical references (p. 115-121).Complementary-Metal-Oxide-Semiconductor (CMOS) feature size scaling has resulted in significant improvements in the performance and energy efficiency of integrated circuits in the past 4 decades. However, in the last decade and for technology nodes below 90 nm, the scaling of threshold and supply voltages has slowed, as a result of subthreshold leakage, and power density has increased with each new technology node. This has forced a move toward multi-core architectures, but the energy efficiency benefits of parallelism are limited by the sub-thresahold leakage and the minimum energy point for a given function. Avoiding this roadblock requires an alternative device with more ideal switching characteristics. One promising class of such devices is the electro-statically actuated micro-electro-mechanical (MEM) relay which offers zero leakage current and abrupt turn-on behavior. Although a MEM relay is inherently slower than a CMOS transistor due to the mechanical movement, we have developed circuit design methodologies to mitigate this problem at the system level. This thesis explores such design optimization techniques and investigates the viability of MEM relays as an alternative switching technology for very-large scale integration (VLSI) applications. In the first part of this thesis, the feasibility of MEM relays for power management applications is discussed. Due to their negligibly low leakage, in certain applications, chips utilizing power gates built with MEM relays can achieve lower total energy than those built with CMOS transistors. A simple comparative analysis is presented and provides design guidelines and energy savings estimates as a function of technology parameters, and quantifies the further benefits of scaled relay designs. We also demonstrate a relay chip successfully power-gating a CMOS chip, and show a relay-based pulse generator suitable for self-timed operation. Going beyond power-gating applications, this work also describes circuit techniques and trade-offs for logic design with MEM-relays, focusing on multipliers which are commonly known as the most complex arithmetic units in a digital system. These techniques leverage the large disparity between mechanical and electrical time-constants of a relay, partitioning the logic into large, complex gates to minimize the effect of mechanical delay and improve circuit performance. At the component design level, innovations in compressor unit design minimize the required number of relays for each block and facilitate component cascading with no delay penalty. We analyze the area/energy/delay trade-offs vs. CMOS designs, for typical bit-widths, and show that scaled relays offer 10-20x lower energy per operation for moderate throughputs (<10-100MOPS). In addition to this analysis, we demonstrate the functionality of some of the most complex MEM relay circuits reported to date. Finally, considering the importance of signal generation and transmission in VLSI systems, this thesis presents MEM relay-based I/O units, focusing on design and demonstration of digital to analog converters (DAC). It also explores the concept of faster-than-mechanical-delay signal transmission.by Hossein Fariborzi.Ph.D