A 14mW 2.5MS/s 14bit Sigma-Delta Modulator Using Pseudo- Differential Split-Path Cascode Amplifiers

Abstract—Switched-capacitor biased pseudo-differential split-path cascode amplifiers are proposed to achieve high power efficiency and small die area for a 14-bit 2.5MS/s Σ∆ modulator. Sufficient power supply rejection is maintained through the biasing circuit. A novel signal and reference sampling network eliminates input common-mode voltages and relaxes op-amp linearity requirements, making it possible to use short channel length transistors for speed and power efficiency. A prototype chip is fabricated in a 0.25µm CMOS technology with a core area of 0.27mm 2. Experimental results show that 84dB dynamic range is achieved with the 1.25MHz signal bandwidth when clocked at 120MHz. The power dissipation is 14mW at 2.5V including the on-chip voltage reference buffers. I