Ultra-Low-Temperature Silicon and Germanium-on-Silicon Avalanche Photodiodes:Modeling, Design, and Characterization

In this thesis we propose the use of photodiodes fabricated in planar technologies to address the detection problem in these applications. A number of solutions exist, optimized for these wavelengths, based on Germanium (Ge) and other III-V materials. In this thesis we focused on Ge thanks to its versatility and ease to use in the clean room. The main advantage of this material is in fact a good compatibility with Silicon and standard CMOS processes. Note that the proposed technology is not based on Silicon/Germanium (SiGe), whereby Ge is used to strain Si to achieve higher bandwidth in Si, not higher sensitivity. In our pure Ge approach, Ge is grafted onto Si (Ge-on-Si), achieving high responsivity at wavelengths of 900nm and higher. The proposed devices can operate in avalanche mode (avalanche photodiodes - APDs), and in Geiger mode (Geiger mode APDs (GAPDs) or single-photon avalanche diodes (SPADs)). To combine the advantages of Ge with single-photon sensitivity and excellent timing resolution of Si-based SPADs, this thesis proposes a new generation of SPADs, achieved in collaboration with Prof. Nanver at TUDelft, aimed at near-infrared range. The fabrication process of the Ge-on-Si SPAD approach, which we are investigating together with the TUDelft group, consists of a standard CMOS process combined with post-processing steps to grow Ge on top of a Si/SiO2 layer. In our study we have investigated the potential for a new generation of massively parallel, Ge-on-Si sensors fabricated in fully CMOS compatible technology. The objective was to address the next challenges of super-parallel pixel arrays, while exploiting the advantages of Ge substrate. The key technology developed in the thesis is a selective chemical-vapor deposition (CVD) epitaxial growth. A novel processing procedure was developed for the p+ Ge surface doping by a sequence of pure-Ga and pure-B depositions (PureGaB). The resulting p+n diodes have exceptionally good I-V characteristics with ideality factor of ~1.1 and low saturation currents. They can be operated both in proportional and in Geiger mode, and exhibit relatively low dark counts. We also looked at techniques to improve red and infrared sensitivity in conventional deep-submicron CMOS processes, by careful selection of standard layers at high depths in the Si substrate. Using the proposed approach, 12 µm-diameter SPADs were fabricated in 0.18µm CMOS technology showing low dark count rates (363 cps) at room temperature and considerably lower rates at cryogenic temperatures (77 K), while the FWHM timing jitter is as low as 76 ps. That of cryogenic SPADs is a novel research direction and in this thesis it was advocated as a significant trend for the future of optical sensing, especially in mid-infrared wavelengths. Low temperature characterizations reported in this thesis exposed how the relevant properties of fabrication materials, such as strength, thermal conductivity, ductility, and electrical resistance are changing. One of the most important properties is superconductivity in materials cooled to extreme temperatures: this is an important trend that will be pursued in the future activities of our group

Miniature high dynamic range time-resolved CMOS SPAD image sensors

Since their integration in complementary metal oxide (CMOS) semiconductor technology in 2003, single photon avalanche diodes (SPADs) have inspired a new era of low cost high integration quantum-level image sensors. Their unique feature of discerning single photon detections, their ability to retain temporal information on every collected photon and their amenability to high speed image sensor architectures makes them prime candidates for low light and time-resolved applications. From the biomedical field of fluorescence lifetime imaging microscopy (FLIM) to extreme physical phenomena such as quantum entanglement, all the way to time of flight (ToF) consumer applications such as gesture recognition and more recently automotive light detection and ranging (LIDAR), huge steps in detector and sensor architectures have been made to address the design challenges of pixel sensitivity and functionality trade-off, scalability and handling of large data rates. The goal of this research is to explore the hypothesis that given the state of the art CMOS nodes and fabrication technologies, it is possible to design miniature SPAD image sensors for time-resolved applications with a small pixel pitch while maintaining both sensitivity and built -in functionality. Three key approaches are pursued to that purpose: leveraging the innate area reduction of logic gates and finer design rules of advanced CMOS nodes to balance the pixel’s fill factor and processing capability, smarter pixel designs with configurable functionality and novel system architectures that lift the processing burden off the pixel array and mediate data flow. Two pathfinder SPAD image sensors were designed and fabricated: a 96 × 40 planar front side illuminated (FSI) sensor with 66% fill factor at 8.25μm pixel pitch in an industrialised 40nm process and a 128 × 120 3D-stacked backside illuminated (BSI) sensor with 45% fill factor at 7.83μm pixel pitch. Both designs rely on a digital, configurable, 12-bit ripple counter pixel allowing for time-gated shot noise limited photon counting. The FSI sensor was operated as a quanta image sensor (QIS) achieving an extended dynamic range in excess of 100dB, utilising triple exposure windows and in-pixel data compression which reduces data rates by a factor of 3.75×. The stacked sensor is the first demonstration of a wafer scale SPAD imaging array with a 1-to-1 hybrid bond connection. Characterisation results of the detector and sensor performance are presented. Two other time-resolved 3D-stacked BSI SPAD image sensor architectures are proposed. The first is a fully integrated 5-wire interface system on chip (SoC), with built-in power management and off-focal plane data processing and storage for high dynamic range as well as autonomous video rate operation. Preliminary images and bring-up results of the fabricated 2mm² sensor are shown. The second is a highly configurable design capable of simultaneous multi-bit oversampled imaging and programmable region of interest (ROI) time correlated single photon counting (TCSPC) with on-chip histogram generation. The 6.48μm pitch array has been submitted for fabrication. In-depth design details of both architectures are discussed