Scaling the bulk-driven MOSFET into deca-nanometer bulk CMOS technologies

The International Technology Roadmap for Semiconductors predicts that the nominal power supply voltage, VDD, will fall to 0.7 V by the end of the bulk CMOS era. At that time, it is expected that the long-channel threshold voltage of a MOSFET, VT0, will rise to 35.5% of VDD in order to maintain acceptable off-state leakage characteristics in digital systems. Given the recent push for system-on-a-chip integration, this increasing trend in VT0/VDD poses a serious threat to the future of analog design because it causes traditional analog circuit topologies to experience progressively problematic signal swing limitations in each new process generation. To combat the process-scaling-induced signal swing limitations of analog circuitry, researchers have proposed the use of bulk-driven MOSFETs. By using the bulk terminal as an input rather than the gate, the bulk-driven MOSFET makes it possible to extend the applicability of any analog cell to extremely low power supply voltages because VT0 does not appear in the device\u27s input signal path. Since the viability of the bulk-driven technique was first investigated in a 2 um p-well process, there have been numerous reports of low-voltage analog designs incorporating bulk-driven MOSFETs in the literature - most of which appear in technologies with feature sizes larger than 0.18 um. However, as of yet, no effort has been undertaken to understand how sub-micron process scaling trends have influenced the performance of a bulk-driven MOSFET, let alone make the device more adaptable to the deca-nanometer technologies widely used in the analog realm today. Thus, to further the field\u27s understanding of the bulk-driven MOSFET, this dissertation aims to examine the implications of scaling the device into a standard 90 nm bulk CMOS process. This dissertation also describes how the major disadvantages of a bulk-driven MOSFET - i.e., its reduced intrinsic gain, its limited frequency response and its large layout area requirement - can be mitigated through modifications to the device\u27s vertical doping profile and well structure. To gauge the potency of the proposed process changes, an optimized n-type bulk-driven MOSFET has been designed in a standard 90 nm bulk CMOS process via the 2-D device simulator, ATLAS

Variability-aware design of CMOS nanopower reference circuits

Questo lavoro è inserito nell'ambito della progettazione di circuiti microelettronici analogici con l'uso di tecnologie scalate, per le quali ha sempre maggiore importanza il problema della sensibilità delle grandezze alle variazioni di processo. Viene affrontata la progettazione di generatori di quantità di riferimento molto precisi, basati sull’uso di dispositivi che sono disponibili anche in tecnologie CMOS standard e che sono “intrinsecamente” più robusti rispetto alle variazioni di processo. Questo ha permesso di ottenere una bassa sensibilità al processo insieme ad un consumo di potenza estremamente ridotto, con il principale svantaggio di una elevata occupazione di area. Tutti i risultati sono stati ottenuti in una tecnologia 0.18μm CMOS. In particolare, abbiamo progettato un riferimento di tensione, ottenendo una deviazione standard relativa della tensione di riferimento dello 0.18% e un consumo di potenza inferiore a 70 nW, sulla base di misure su un set di 20 campioni di un singolo batch. Sono anche disponibili risultati relativi alla variabilità inter batch, che mostrano una deviazione standard relativa cumulativa della tensione di riferimento dello 0.35%. Abbiamo quindi progettato un riferimento di corrente, ottenendo anche in questo caso una sensibilità al processo della corrente di riferimento dell’1.4% con un consumo di potenza inferiore a 300 nW (questi sono risultati sperimentali ottenuti dalle misure su 20 campioni di un singolo batch). I riferimenti di tensione e di corrente proposti sono stati quindi utilizzati per la progettazione di un oscillatore a rilassamento a bassa frequenza, che unisce una ridotta sensibilità al processo, inferiore al 2%, con un basso consumo di potenza, circa 300 nW, ottenuto sulla base di simulazioni circuitali. Infine, nella progettazione dei blocchi sopra menzionati, abbiamo applicato un metodo per la determinazione della stabilità dei punti di riposo, basato sull’uso dei CAD standard utilizzati per la progettazione microelettronica. Questo approccio ci ha permesso di determinare la stabilità dei punti di riposo desiderati, e ci ha anche permesso di stabilire che i circuiti di start up spesso non sono necessari

ENABLING HARDWARE TECHNOLOGIES FOR AUTONOMY IN TINY ROBOTS: CONTROL, INTEGRATION, ACTUATION

The last two decades have seen many exciting examples of tiny robots from a few cm3 to less than one cm3. Although individually limited, a large group of these robots has the potential to work cooperatively and accomplish complex tasks. Two examples from nature that exhibit this type of cooperation are ant and bee colonies. They have the potential to assist in applications like search and rescue, military scouting, infrastructure and equipment monitoring, nano-manufacture, and possibly medicine. Most of these applications require the high level of autonomy that has been demonstrated by large robotic platforms, such as the iRobot and Honda ASIMO. However, when robot size shrinks down, current approaches to achieve the necessary functions are no longer valid. This work focused on challenges associated with the electronics and fabrication. We addressed three major technical hurdles inherent to current approaches: 1) difficulty of compact integration; 2) need for real-time and power-efficient computations; 3) unavailability of commercial tiny actuators and motion mechanisms. The aim of this work was to provide enabling hardware technologies to achieve autonomy in tiny robots. We proposed a decentralized application-specific integrated circuit (ASIC) where each component is responsible for its own operation and autonomy to the greatest extent possible. The ASIC consists of electronics modules for the fundamental functions required to fulfill the desired autonomy: actuation, control, power supply, and sensing. The actuators and mechanisms could potentially be post-fabricated on the ASIC directly. This design makes for a modular architecture. The following components were shown to work in physical implementations or simulations: 1) a tunable motion controller for ultralow frequency actuation; 2) a nonvolatile memory and programming circuit to achieve automatic and one-time programming; 3) a high-voltage circuit with the highest reported breakdown voltage in standard 0.5 μm CMOS; 4) thermal actuators fabricated using CMOS compatible process; 5) a low-power mixed-signal computational architecture for robotic dynamics simulator; 6) a frequency-boost technique to achieve low jitter in ring oscillators. These contributions will be generally enabling for other systems with strict size and power constraints such as wireless sensor nodes