Low-power and high-performance SRAM design in high variability advanced CMOS technology

As process technologies shrink, the size and number of memories on a chip are exponentially increasing. Embedded SRAMs are a critical component in modern digital systems, and they strongly impact the overall power, performance, and area. To promote memory-related research in academia, this dissertation introduces OpenRAM, a flexible, portable and open-source memory compiler and characterization methodology for generating and verifying memory designs across different technologies.In addition, SRAM designs, focusing on improving power consumption, access time and bitcell stability are explored in high variability advanced CMOS technologies. To have a stable read/write operation for SRAM in high variability process nodes, a differential-ended single-port 8T bitcell is proposed that improves the read noise margin, write noise margin and readout bitcell current by 45%, 48% and 21%, respectively, compared to a conventional 6T bitcell. Also, a differential-ended single-port 12T bitcell for subthreshold operation is proposed that solves the half-select disturbance and allows efficient bit-interleaving. 12T bitcell has a leakage control mechanism which helps to reduce the power consumption and provides operation down to 0.3 V. Both 8T and 12T bitcells are analyzed in a 64 kb SRAM array using 32 nm technology. Besides, to further improve the access time and power consumption, two tracking circuits (multi replica bitline delay and reconfigurable replica bitline delay techniques) are proposed to aid the generation of accurate and optimum sense amplifier set time.An error tolerant SRAM architecture suitable for low voltage video application with dynamic power-quality management is also proposed in this dissertation. This memory uses three power supplies to improve the SRAM stability in low voltages. The proposed triple-supply approach achieves 63% improvement in image quality and 69% reduction in power consumption compared to a single-supply 64 kb SRAM array at 0.70 V

A 0.4 V 12T 2RW dual-port SRAM with suppressed common-row-access disturbance

Dual-port SRAMs with two sets of address bus and data IOs are widely employed in various applications to increase throughput. Conventional 8T dual-port SRAM suffers reliability issue at low voltages due to common-row-access disturbance. Specifically, a row is simultaneously accessed by two operations, which can flip existing data and cause incorrect read output. Previous work can address this stability issue by assisting circuitry at cost of timing. This paper presents a low voltage 12T 2RW SRAM featuring parallel access with suppressed disturbance to ameliorate the problem without performance degradation. The proposed SRAM cell suppresses the disturbance by separating read path from internal nodes and minimizing the probability of the worst case stability with area penalty of 6%. In addition, hierarchical bitlines and a virtual ground technique are employed to further lower the minimum operating voltage and power consumption. A 16 kb SRAM has been fabricated in a 65 nm CMOS technology and extended the operating voltage from super-threshold region to 0.4 V at common-row-access scenario.ASTAR (Agency for Sci., Tech. and Research, S’pore)Accepted versio