2 research outputs found
์ ์ ๋ ฅ, ์ ๋ฉด์ ์ ์ ์ก์์ ๊ธฐ ์ค๊ณ๋ฅผ ์ํ ํ๋ก ๊ธฐ์
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ผ๋ฌธ (๋ฐ์ฌ)-- ์์ธ๋ํ๊ต ๋ํ์ : ์ ๊ธฐยท์ปดํจํฐ๊ณตํ๋ถ, 2016. 8. ์ ๋๊ท .In this thesis, novel circuit techniques for low-power and area-efficient wireline transceiver, including a phase-locked loop (PLL) based on a two-stage ring oscillator, a scalable voltage-mode transmitter, and a forwarded-clock (FC) receiver based on a delay-locked-loop (DLL) based per-pin deskew, are proposed.
At first, a two-stage ring PLL that provides a four-phase, high-speed clock for a quarter-rate TX in order to minimize power consumption is presented. Several analyses and verification techniques, ranging from the clocking architectures for a high-speed TX to oscillation failures in a two-stage ring oscillator, are addressed in this thesis. A tri-state-inverterโbased frequency-divider and an AC-coupled clock-buffer are used for high-speed operations with minimal power and area overheads. The proposed PLL fabricated in the 65-nm CMOS technology occupies an active area of 0.009 mm2 with an integrated-RMS-jitter of 414 fs from 10 kHz to 100 MHz while consuming 7.6 mW from a 1.2-V supply at 10 GHz. The resulting figure-of-merit is -238.8 dB, which surpasses that of the state-of-the-art ring-PLLs by 4 dB.
Secondly, a voltage-mode (VM) transmitter which offers a wide operation range of 6 to 32 Gb/s, controllable pre-emphasis equalization and output voltage swing without altering output impedance, and a power supply scalability is presented. A quarter-rate clocking architecture is employed in order to maximize the scalability and energy efficiency across the variety of operating conditions. A P-over-N VM driver is used for CMOS compatibility and wide voltage-swing range required for various I/O standards. Two supply regulators calibrate the output impedance of the VM driver across the wide swing and pre-emphasis range. A single phase-locked loop is used to provide a wide frequency range of 1.5-to-8 GHz. The prototype chip is fabricated in 65-nm CMOS technology and occupies active area of 0.48x0.36 mm2. The proposed transmitter achieves 250-to-600-mV single-ended swing and exhibits the energy efficiency of 2.10-to-2.93 pJ/bit across the data rate of 6-to-32 Gb/s.
And last, this thesis describes a power and area-efficient FC receiver and includes an analysis of the jitter tolerance of the FC receiver. In the proposed design, jitter tolerance is maximized according to the analysis by employing a DLL-based de-skewing. A sample-swapping bang-bang phase-detector (SS-BBPD) eliminates the stuck locking caused by the finite delay range of the voltage-controlled delay line (VCDL), and also reduces the required delay range of the VCDL by half. The proposed FC receiver is fabricated in 65-nm CMOS technology and occupies an active area of 0.025 mm2. At a data rate of 12.5 Gb/s, the proposed FC receiver exhibits an energy efficiency of 0.36 pJ/bit, and tolerates 1.4-UIpp sinusoidal jitter of 300 MHz.Chapter 1. Introduction 1
1.1. Motivation 1
1.2. Thesis organization 5
Chapter 2. Phase-Locked Loop Based on Two-Stage Ring Oscillator 7
2.1. Overivew 7
2.2. Background and Analysis of a Two-stage Ring Oscillator 11
2.3. Circuit Implementation of The Proposed PLL 25
2.4. Measurement Results 33
Chapter 3. A Scalable Voltage-Mode Transmitter 37
3.1. Overview 37
3.2. Design Considerations on a Scalable Serial Link Transmitter 40
3.3. Circuit Implementation 46
3.4. Measurement Results 56
Chapter 4. Delay-Locked Loop Based Forwarded-Clock Receiver 62
4.1. Overview 62
4.2. Timing and Data Recovery in a Serial Link 65
4.3. DLL-Based Forwarded-Clock Receiver Characteristics 70
4.4. Circuit Implementation 79
4.5. Measurement Results 89
Chapter 5. Conclusion 94
Appendix 96
Appendix A. Design flow to optimize a high-speed ring oscillator 96
Appendix B. Reflection Issues in N-over-N Voltage-Mode Driver 99
Appendix C. Analysis on output swing and power consumption of the P-over-N voltage-mode driver 107
Appendix D. Loop Dynamics of DLL 112
Bibliography 121
Abstract 128Docto