Sub-1 V, 4 nA CMOS voltage references with digitally-trimmable temperature coefficient

Voltage references are fundamental to mixed signal converters which are widely used in elec- tronics. Hence there are signicant advantages in having the voltage reference operate with less power while minimizing area consumption and maintaining performance. Past designs have suered from issues related to process variations which adversely aect the temperature coe- cient of the circuit output. To compensate for these process variations, a means to modify the temperature coecient are proposed and experimentally veried with two circuit architectures. Five test chip samples implement these architectures in a 0.35 m CMOS process. Design methodologies for both architectures are presented. Design techniques include the use of a high-swing cascode to improve Line Sensitivity while minimizing additional power consumption, accounting for a well-matched layout, and the eect of leakage currents on the performance of the circuit. Layout schematics, performance gures, test methodologies and results are presented. Each circuit dissipates less than 4 nW and operates down to 0.9 V or better with Line Sensitivity and Power Supply Rejection Ratio of less than 0.15 %/V and -58 dB respectively, while consuming an area of 0.053 mm2 or less. The experimental average and median temperature coecient was less than 26 ppm/C and 22 ppm/C respectively in the 􀀀20 C to 80 C range, with the best performance being less than 8.1 ppm/C. Areas of improvement and potential areas of future research are then identied to facilitate advancement of this work

Integrated Circuits for Programming Flash Memories in Portable Applications

Smart devices such as smart grids, smart home devices, etc. are infrastructure systems that connect the world around us more than before. These devices can communicate with each other and help us manage our environment. This concept is called the Internet of Things (IoT). Not many smart nodes exist that are both low-power and programmable. Floating-gate (FG) transistors could be used to create adaptive sensor nodes by providing programmable bias currents. FG transistors are mostly used in digital applications like Flash memories. However, FG transistors can be used in analog applications, too. Unfortunately, due to the expensive infrastructure required for programming these transistors, they have not been economical to be used in portable applications. In this work, we present low-power approaches to programming FG transistors which make them a good candidate to be employed in future wireless sensor nodes and portable systems. First, we focus on the design of low-power circuits which can be used in programming the FG transistors such as high-voltage charge pumps, low-drop-out regulators, and voltage reference cells. Then, to achieve the goal of reducing the power consumption in programmable sensor nodes and reducing the programming infrastructure, we present a method to program FG transistors using negative voltages. We also present charge-pump structures to generate the necessary negative voltages for programming in this new configuration

A fully-integrated 180 nm CMOS 1.2 V low-dropout regulator for low-power portable applications

This paper presents the design and postlayout simulation results of a capacitor-less low dropout (LDO) regulator fully integrated in a low-cost standard 180 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology which regulates the output voltage at 1.2 V from a 3.3 to 1.3 V battery over a -40 to 120 degrees C temperature range. To meet with the constraints of system-on-chip (SoC) battery-operated devices, ultralow power (I-q = 8.6 mu A) and minimum area consumption (0.109 mm(2)) are maintained, including a reference voltage V-ref = 0.4 V. It uses a high-gain dynamically biased folded-based error amplifier topology optimized for low-voltage operation that achieves an enhanced regulation-fast transient performance trade-off

Design and Implementation of Low Power SRAM Using Highly Effective Lever Shifters

The explosive growth of battery-operated devices has made low-power design a priority in recent years. In high-performance Systems-on-Chip, leakage power consumption has become comparable to the dynamic component, and its relevance increases as technology scales. These trends are even more evident for SRAM memory devices since they are a dominant source of standby power consumption in low-power application processors. The on-die SRAM power consumption is particularly important for increasingly pervasive mobile and handheld applications where battery life is a key design and technology attribute. In the SRAM-memory design, SRAM cells also comprise the most significant portion of the total chip. Moreover, the increasing number of transistors in the SRAM memories and the MOSs\u27 increasing leakage current in the scaled technologies have turned the SRAM unit into a power-hungry block for both dynamic and static viewpoints. Although the scaling of the supply voltage enables low-power consumption, the SRAM cells\u27 data stability becomes a major concern. Thus, the reduction of SRAM leakage power has become a critical research concern. To address the leakage power consumption in high-performance cache memories, a stream of novel integrated circuit and architectural level techniques are proposed by researchers including leakage-current management techniques, cell array leakage reduction techniques, bitline leakage reduction techniques, and leakage current compensation techniques. The main goal of this work was to improve the cell array leakage reduction techniques in order to minimize the leakage power for SRAM memory design in low-power applications. This study performs the body biasing application to reduce leakage current as well. To adjust the NMOSs\u27 threshold voltage and consequently leakage current, a negative DC voltage could be applied to their body terminal as a second gate. As a result, in order to generate a negative DC voltage, this study proposes a negative voltage reference that includes a trimming circuit and a negative level shifter. These enhancements are employed to a 10kb SRAM memory operating at 0.3V in a 65nm CMOS process

Referências de tensão integradas CMOS : testes, medidas e caracterização térmica

Este trabalho descreve o setup de medidas e os resultados experimentais de uma Referência de Tensão somente com transistores NMOS baseada no ponto ZTC. Os transistores Zero- VT são usados como cargas ativas no circuito aberto e de feedback do circuito. Os resultados de medição de 10 amostras (processo 130 nm CMOS) do mesmo lote mostram que o circuito pode operar em 0,6 V de tensão mínima de alimentação, produz um Vref 0,372 V com 3 mV de desvio padrão, em comparação com 0,450 V e 29,2 mV respectivamente da simulação pós-layout. Além disso, o circuito ocupa uma área de apenas 0,006 mm 2. O coeficiente de temperatura medido de -55 oC a 75 oC é 76 ppm / oC para alimentação nominal de 1,2 V. O consumo de energia à temperatura ambiente e a alimentação de 1,2 V é de cerca de 0,9 μW. O circuito atinge um line sensitivity de apenas 0.177 % / V. O PSR foi medido em 500 Hz, 1 Khz, 10Khz e 100Khz e os resultados foram -27,5 dB, -23,5, -11,5 e -9,42 respectivamente.This work describes the measurement setup and results of NMOS-Only Voltage Reference based on the Zero Temperature Coefficient (ZTC) transistor point. Zero-VT transistors are used as active loads in the open and feedback loop of the circuit. Measurement results from 10 samples (130 nm CMOS process) of the same batch shows that circuit can operate at 0.6 minimum supply voltage, produces a Vref of 0.372 V with 3 mV of standard deviation, in comparison of 0.450 V and 29.2 mV respectively for post-layout simulation. Also the circuit occupy a 0.006 mm2 area. Measured temperature coefficient from -55 oC to 75 oC is 76 ppm/oC for nominal 1.2 V supply. Power consumption at room temperature and 1.2 V supply is around 0.9 μW. The circuit achieve a line sensitivity of only 0.177 %/V. The PSR was measured in 500 Hz, 1 Khz, 10Khz and 100Khz and the results was -27.5 dB, -23.5, -11.5 and -9.42 respectively

Régulateurs "Waterfall" : une nouvelle topologie énergétique pour l'électronique

Ce travail décrit une nouvelle topologie d'alimentation qui apporte des bénéfices aux dispositifs portables et aux composants électroniques à faible consommation. À l'autre extrémité du spectre, il serait également applicable aux systèmes à tension de bus plus élevée, tels que les panneaux solaires et les véhicules électriques, qui doivent décomposer des tensions plus élevées en domaines utilisables. La nouvelle topologie, que nous avons nommée Waterfall regulator, est décrite dans le présent travail et nommée ainsi pour ses caractéristiques saillantes rappelant une chute en cascade. Ce dispositif ouvre de nouvelles perspectives pour les systèmes à très basse consommation, basse tension et courant faible. Le mode de fonctionnement consiste à diviser une source d'alimentation brute en plusieurs domaines de tension, qui peuvent ensuite être utilisés pour alimenter les éléments individuels d'un système ou plusieurs unités indépendantes. Nous décrivons ici le premier rapport sur la réussite de la version de recyclage de l'énergie de ce nouveau système. Le dispositif se caractérise par une série de régulateurs de tension à faible chute et de circuits de déversement de courant (pass MOSFET). Le régulateur partage le courant qui traverse sa charge respective et complète le courant du stade suivant par un déversoir de courant, selon les besoins. Le contrôle s'effectue via une architecture de contrôle en cascade et peut être étendu à des périphériques d'ordre supérieur.This work described a new power supply topology that benefits portable device and low power electronics. At the other end of the spectrum, it is also applicable to higher bus voltage systems like solar panels and electric vehicles that must split higher voltages into usable domains. The new topology, which we named waterfall regulator, is describe herein and named as such for its salient features reminiscent of a waterfall. It opens up a new realm of possibilities for supra low power, low voltage and low current systems. The mode of operation consists of splitting a raw supply source into smaller voltage domains which can then be used for powering individual element of a system or powering multiple independent units. We describe here the first report of successful energy recycling version of this novel system. The devices are composed of a series of low dropout voltage regulators and current spillways circuits (pass MOSFET). The regulators share current passing thought their respective load and supplement current through a current spillway as required. Control is achieved through a cascade architecture and can be scaled up to higher order devices